Merge pull request #3478 from vargaz/fix-pedump

[mono.git] / mono / mini / mini-arm.c

diff --git a/mono/mini/mini-arm.c b/mono/mini/mini-arm.c
index 8b48bc98fd3e95aedc60133921e5a72ee42fed28..7b2e1fa7b48e2438c7e85deeb87108be375a6936 100644 (file)
--- a/mono/mini/mini-arm.c
+++ b/mono/mini/mini-arm.c
@@ -18,7 +18,7 @@
 #include <mono/metadata/profiler-private.h>
 #include <mono/metadata/debug-helpers.h>
 #include <mono/utils/mono-mmap.h>
-#include <mono/utils/mono-hwcap-arm.h>
+#include <mono/utils/mono-hwcap.h>
 #include <mono/utils/mono-memory-model.h>
 #include <mono/utils/mono-threads-coop.h>
 
@@ -4442,14 +4442,12 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
                                ARM_DMB (code, ARM_DMB_SY);
                        break;
                }
-               /*case OP_BIGMUL:
-                       ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
-                       ppc_mulhw (code, ppc_r3, ins->sreg1, ins->sreg2);
+               case OP_BIGMUL:
+                       ARM_SMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
                        break;
                case OP_BIGMUL_UN:
-                       ppc_mullw (code, ppc_r4, ins->sreg1, ins->sreg2);
-                       ppc_mulhwu (code, ppc_r3, ins->sreg1, ins->sreg2);
-                       break;*/
+                       ARM_UMULL_REG_REG (code, ins->backend.reg3, ins->dreg, ins->sreg1, ins->sreg2);
+                       break;
                case OP_STOREI1_MEMBASE_IMM:
                        code = mono_arm_emit_load_imm (code, ARMREG_LR, ins->inst_imm & 0xFF);
                        g_assert (arm_is_imm12 (ins->inst_offset));
@@ -4629,6 +4627,7 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
                                g_assert (((guint64)(gsize)ss_trigger_page >> 32) == 0);
                        }
 
+                       /* Single step check */
                        if (ins->flags & MONO_INST_SINGLE_STEP_LOC) {
                                if (cfg->soft_breakpoints) {
                                        /* Load the address of the sequence point method variable. */
@@ -4663,6 +4662,7 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
 
                        mono_add_seq_point (cfg, bb, ins, code - cfg->native_code);
 
+                       /* Breakpoint check */
                        if (cfg->compile_aot) {
                                guint32 offset = code - cfg->native_code;
                                guint32 val;
@@ -6543,22 +6543,36 @@ mono_arch_emit_prolog (MonoCompile *cfg)
        if (cfg->arch.seq_point_ss_method_var) {
                MonoInst *ss_method_ins = cfg->arch.seq_point_ss_method_var;
                MonoInst *bp_method_ins = cfg->arch.seq_point_bp_method_var;
+
                g_assert (ss_method_ins->opcode == OP_REGOFFSET);
                g_assert (arm_is_imm12 (ss_method_ins->inst_offset));
-               g_assert (bp_method_ins->opcode == OP_REGOFFSET);
-               g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
 
-               ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
-               ARM_B (code, 1);
-               *(gpointer*)code = &single_step_tramp;
-               code += 4;
-               *(gpointer*)code = breakpoint_tramp;
-               code += 4;
+               if (cfg->compile_aot) {
+                       MonoInst *info_var = cfg->arch.seq_point_info_var;
+                       int dreg = ARMREG_LR;
 
-               ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
-               ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
-               ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
-               ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
+                       g_assert (info_var->opcode == OP_REGOFFSET);
+                       g_assert (arm_is_imm12 (info_var->inst_offset));
+
+                       ARM_LDR_IMM (code, dreg, info_var->inst_basereg, info_var->inst_offset);
+                       ARM_LDR_IMM (code, dreg, dreg, MONO_STRUCT_OFFSET (SeqPointInfo, ss_tramp_addr));
+                       ARM_STR_IMM (code, dreg, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
+               } else {
+                       g_assert (bp_method_ins->opcode == OP_REGOFFSET);
+                       g_assert (arm_is_imm12 (bp_method_ins->inst_offset));
+
+                       ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
+                       ARM_B (code, 1);
+                       *(gpointer*)code = &single_step_tramp;
+                       code += 4;
+                       *(gpointer*)code = breakpoint_tramp;
+                       code += 4;
+
+                       ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 0);
+                       ARM_STR_IMM (code, ARMREG_IP, ss_method_ins->inst_basereg, ss_method_ins->inst_offset);
+                       ARM_LDR_IMM (code, ARMREG_IP, ARMREG_LR, 4);
+                       ARM_STR_IMM (code, ARMREG_IP, bp_method_ins->inst_basereg, bp_method_ins->inst_offset);
+               }
        }
 
        cfg->code_len = code - cfg->native_code;
@@ -7400,6 +7414,7 @@ mono_arch_get_seq_point_info (MonoDomain *domain, guint8 *code)
 
                info->ss_trigger_page = ss_trigger_page;
                info->bp_trigger_page = bp_trigger_page;
+               info->ss_tramp_addr = &single_step_tramp;
 
                mono_domain_lock (domain);
                g_hash_table_insert (domain_jit_info (domain)->arch_seq_points,