#include "inssel.h"
#include "cpu-arm.h"
#include "trace.h"
+#ifdef ARM_FPU_FPA
#include "mono/arch/arm/arm-fpa-codegen.h"
+#elif defined(ARM_FPU_VFP)
+#include "mono/arch/arm/arm-vfp-codegen.h"
+#endif
+
+static int v5_supported = 0;
+static int thumb_supported = 0;
+
+static int mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount);
/*
* TODO:
return code;
}
+static guint8*
+emit_call_reg (guint8 *code, int reg)
+{
+ if (v5_supported) {
+ ARM_BLX_REG (code, reg);
+ } else {
+ ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
+ if (thumb_supported)
+ ARM_BX (code, reg);
+ else
+ ARM_MOV_REG_REG (code, ARMREG_PC, reg);
+ }
+ return code;
+}
+
/*
* mono_arch_get_argument_info:
* @csig: a method signature
mono_arch_cpu_optimizazions (guint32 *exclude_mask)
{
guint32 opts = 0;
+ char buf [512];
+ char *line;
+ FILE *file = fopen ("/proc/cpuinfo", "r");
+ if (file) {
+ while ((line = fgets (buf, 512, file))) {
+ if (strncmp (line, "Processor", 9) == 0) {
+ char *ver = strstr (line, "(v");
+ if (ver && (ver [2] == '5' || ver [2] == '6' || ver [2] == '7')) {
+ v5_supported = TRUE;
+ }
+ continue;
+ }
+ if (strncmp (line, "Features", 8) == 0) {
+ char *th = strstr (line, "thumb");
+ if (th) {
+ thumb_supported = TRUE;
+ if (v5_supported)
+ break;
+ }
+ continue;
+ }
+ }
+ fclose (file);
+ /*printf ("features: v5: %d, thumb: %d\n", v5_supported, thumb_supported);*/
+ }
/* no arm-specific optimizations yet */
*exclude_mask = 0;
enum {
RegTypeGeneral,
RegTypeBase,
+ RegTypeBaseGen,
RegTypeFP,
RegTypeStructByVal,
RegTypeStructByAddr
ainfo->reg = *gr;
}
} else {
- if (*gr > ARMREG_R2) {
+ if (*gr == ARMREG_R3) {
+ /* first word in r3 and the second on the stack */
+ ainfo->offset = *stack_size;
+ ainfo->reg = ARMREG_SP; /* in the caller */
+ ainfo->regtype = RegTypeBaseGen;
+ *stack_size += 4;
+ } else if (*gr > ARMREG_R3) {
/**stack_size += 7;
*stack_size &= ~7;*/
ainfo->offset = *stack_size;
curinst = 0;
if (sig->hasthis) {
- inst = m->varinfo [curinst];
+ inst = m->args [curinst];
if (inst->opcode != OP_REGVAR) {
inst->opcode = OP_REGOFFSET;
inst->inst_basereg = frame_reg;
}
for (i = 0; i < sig->param_count; ++i) {
- inst = m->varinfo [curinst];
+ inst = m->args [curinst];
if (inst->opcode != OP_REGVAR) {
inst->opcode = OP_REGOFFSET;
inst->inst_basereg = frame_reg;
call->used_iregs |= 1 << (ainfo->reg + 1);
if (arg->type == STACK_R8) {
if (ainfo->size == 4) {
+#ifndef MONO_ARCH_SOFT_FLOAT
arg->opcode = OP_OUTARG_R4;
+#endif
} else {
call->used_iregs |= 1 << (ainfo->reg + 1);
}
} else if (ainfo->regtype == RegTypeBase) {
arg->opcode = OP_OUTARG_MEMBASE;
arg->backend.arg_info = (ainfo->offset << 8) | ainfo->size;
+ } else if (ainfo->regtype == RegTypeBaseGen) {
+ call->used_iregs |= 1 << ARMREG_R3;
+ arg->opcode = OP_OUTARG_MEMBASE;
+ arg->backend.arg_info = (ainfo->offset << 8) | 0xff;
+ if (arg->type == STACK_R8)
+ cfg->flags |= MONO_CFG_HAS_FPOUT;
} else if (ainfo->regtype == RegTypeFP) {
arg->backend.reg3 = ainfo->reg;
- /* FPA args are passed in int regs */
+ /* FP args are passed in int regs */
call->used_iregs |= 1 << ainfo->reg;
if (ainfo->size == 8) {
arg->opcode = OP_OUTARG_R8;
code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
ARM_MOV_REG_IMM8 (code, ARMREG_R1, 0); /* NULL ebp for now */
code = mono_arm_emit_load_imm (code, ARMREG_R2, (guint32)func);
- ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
- ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_R2);
+ code = emit_call_reg (code, ARMREG_R2);
return code;
}
cfg->native_code = g_realloc (cfg->native_code, cfg->code_size);
code = cfg->native_code + offset;
}
-handle_enum:
switch (rtype) {
case MONO_TYPE_VOID:
/* special case string .ctor icall */
code = mono_arm_emit_load_imm (code, ARMREG_R0, (guint32)cfg->method);
code = mono_arm_emit_load_imm (code, ARMREG_IP, (guint32)func);
- ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
- ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
+ code = emit_call_reg (code, ARMREG_IP);
switch (save_mode) {
case SAVE_TWO:
if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
ins->inst_basereg == last_ins->inst_destbasereg &&
ins->inst_offset == last_ins->inst_offset) {
- if (ins->dreg == last_ins->sreg1) {
- last_ins->next = ins->next;
- ins = ins->next;
- continue;
- } else {
- //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
- ins->opcode = OP_MOVE;
- ins->sreg1 = last_ins->sreg1;
- }
+ ins->opcode = (ins->opcode == OP_LOADI1_MEMBASE) ? CEE_CONV_I1 : CEE_CONV_U1;
+ ins->sreg1 = last_ins->sreg1;
}
break;
case OP_LOADU2_MEMBASE:
if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
ins->inst_basereg == last_ins->inst_destbasereg &&
ins->inst_offset == last_ins->inst_offset) {
- if (ins->dreg == last_ins->sreg1) {
- last_ins->next = ins->next;
- ins = ins->next;
- continue;
- } else {
- //static int c = 0; printf ("MATCHX %s %d\n", cfg->method->name,c++);
- ins->opcode = OP_MOVE;
- ins->sreg1 = last_ins->sreg1;
- }
+ ins->opcode = (ins->opcode == OP_LOADI2_MEMBASE) ? CEE_CONV_I2 : CEE_CONV_U2;
+ ins->sreg1 = last_ins->sreg1;
}
break;
case CEE_CONV_I4:
static void
mono_arch_lowering_pass (MonoCompile *cfg, MonoBasicBlock *bb)
{
- MonoInst *ins, *next, *temp, *last_ins = NULL;
+ MonoInst *ins, *temp, *last_ins = NULL;
int rot_amount, imm8, low_imm;
/* setup the virtual reg allocator */
- if (bb->max_ireg > cfg->rs->next_vireg)
- cfg->rs->next_vireg = bb->max_ireg;
+ if (bb->max_vreg > cfg->rs->next_vreg)
+ cfg->rs->next_vreg = bb->max_vreg;
ins = bb->code;
while (ins) {
ins->inst_offset = low_imm;
break;
}
- /* FPA doesn't have indexed load instructions */
+ /* VFP/FPA doesn't have indexed load instructions */
g_assert_not_reached ();
break;
case OP_STORE_MEMBASE_REG:
break;
}
/*g_print ("fail with: %d (%d, %d)\n", ins->inst_offset, ins->inst_offset & ~0x1ff, low_imm);*/
- /* FPA doesn't have indexed store instructions */
+ /* VFP/FPA doesn't have indexed store instructions */
g_assert_not_reached ();
break;
case OP_STORE_MEMBASE_IMM:
ins = ins->next;
}
bb->last_ins = last_ins;
- bb->max_ireg = cfg->rs->next_vireg;
+ bb->max_vreg = cfg->rs->next_vreg;
}
emit_float_to_int (MonoCompile *cfg, guchar *code, int dreg, int sreg, int size, gboolean is_signed)
{
/* sreg is a float, dreg is an integer reg */
+#ifdef ARM_FPU_FPA
ARM_FIXZ (code, dreg, sreg);
+#elif defined(ARM_FPU_VFP)
+ if (is_signed)
+ ARM_TOSIZD (code, ARM_VFP_F0, sreg);
+ else
+ ARM_TOUIZD (code, ARM_VFP_F0, sreg);
+ ARM_FMRS (code, dreg, ARM_VFP_F0);
+#endif
if (!is_signed) {
if (size == 1)
ARM_AND_REG_IMM8 (code, dreg, dreg, 0xff);
guchar *code = data;
guint32 *thunks = data;
guint32 *endthunks = (guint32*)(code + bsize);
- int i, count = 0;
+ int count = 0;
int difflow, diffhigh;
/* always ensure a call from pdata->code can reach to the thunks without further thunks */
/* found a free slot instead: emit thunk */
code = (guchar*)thunks;
ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0);
- ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
+ if (thumb_supported)
+ ARM_BX (code, ARMREG_IP);
+ else
+ ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
thunks [2] = (guint32)pdata->target;
mono_arch_flush_icache ((guchar*)thunks, 12);
void
arm_patch (guchar *code, const guchar *target)
{
- guint32 ins = *(guint32*)code;
+ guint32 *code32 = (void*)code;
+ guint32 ins = *code32;
guint32 prim = (ins >> 25) & 7;
- guint32 ovf;
+ guint32 tval = GPOINTER_TO_UINT (target);
//g_print ("patching 0x%08x (0x%08x) to point to 0x%08x\n", code, ins, target);
if (prim == 5) { /* 101b */
/* the diff starts 8 bytes from the branch opcode */
gint diff = target - code - 8;
+ gint tbits;
+ gint tmask = 0xffffffff;
+ if (tval & 1) { /* entering thumb mode */
+ diff = target - 1 - code - 8;
+ g_assert (thumb_supported);
+ tbits = 0xf << 28; /* bl->blx bit pattern */
+ g_assert ((ins & (1 << 24))); /* it must be a bl, not b instruction */
+ /* this low bit of the displacement is moved to bit 24 in the instruction encoding */
+ if (diff & 2) {
+ tbits |= 1 << 24;
+ }
+ tmask = ~(1 << 24); /* clear the link bit */
+ /*g_print ("blx to thumb: target: %p, code: %p, diff: %d, mask: %x\n", target, code, diff, tmask);*/
+ } else {
+ tbits = 0;
+ }
if (diff >= 0) {
if (diff <= 33554431) {
diff >>= 2;
ins = (ins & 0xff000000) | diff;
- *(guint32*)code = ins;
+ ins &= tmask;
+ *code32 = ins | tbits;
return;
}
} else {
if (diff >= -33554432) {
diff >>= 2;
ins = (ins & 0xff000000) | (diff & ~0xff000000);
- *(guint32*)code = ins;
+ ins &= tmask;
+ *code32 = ins | tbits;
return;
}
}
return;
}
-
+ /*
+ * The alternative call sequences looks like this:
+ *
+ * ldr ip, [pc] // loads the address constant
+ * b 1f // jumps around the constant
+ * address constant embedded in the code
+ * 1f:
+ * mov lr, pc
+ * mov pc, ip
+ *
+ * There are two cases for patching:
+ * a) at the end of method emission: in this case code points to the start
+ * of the call sequence
+ * b) during runtime patching of the call site: in this case code points
+ * to the mov pc, ip instruction
+ *
+ * We have to handle also the thunk jump code sequence:
+ *
+ * ldr ip, [pc]
+ * mov pc, ip
+ * address constant // execution never reaches here
+ */
if ((ins & 0x0ffffff0) == 0x12fff10) {
/* branch and exchange: the address is constructed in a reg */
g_assert_not_reached ();
} else {
- guint32 ccode [3];
+ guint32 ccode [4];
guint32 *tmp = ccode;
- ARM_LDR_IMM (tmp, ARMREG_IP, ARMREG_PC, 0);
- ARM_MOV_REG_REG (tmp, ARMREG_LR, ARMREG_PC);
- ARM_MOV_REG_REG (tmp, ARMREG_PC, ARMREG_IP);
+ guint8 *emit = (guint8*)tmp;
+ ARM_LDR_IMM (emit, ARMREG_IP, ARMREG_PC, 0);
+ ARM_MOV_REG_REG (emit, ARMREG_LR, ARMREG_PC);
+ ARM_MOV_REG_REG (emit, ARMREG_PC, ARMREG_IP);
+ ARM_BX (emit, ARMREG_IP);
if (ins == ccode [2]) {
- tmp = (guint32*)code;
- tmp [-1] = (guint32)target;
+ g_assert_not_reached (); // should be -2 ...
+ code32 [-1] = (guint32)target;
return;
}
if (ins == ccode [0]) {
- tmp = (guint32*)code;
- tmp [2] = (guint32)target;
+ /* handles both thunk jump code and the far call sequence */
+ code32 [2] = (guint32)target;
return;
}
g_assert_not_reached ();
* to be used with the emit macros.
* Return -1 otherwise.
*/
-int
+static int
mono_arm_is_rotated_imm8 (guint32 val, gint *rot_amount)
{
guint32 res, i;
while (ins) {
offset = code - cfg->native_code;
- max_len = ((guint8 *)arm_cpu_desc [ins->opcode])[MONO_INST_LEN];
+ max_len = ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
if (offset > (cfg->code_size - max_len - 16)) {
cfg->code_size *= 2;
g_assert (imm8 >= 0);
ARM_CMP_REG_IMM (code, ins->sreg1, imm8, rot_amount);
break;
- case CEE_BREAK:
+ case OP_BREAK:
*(int*)code = 0xe7f001f0;
*(int*)code = 0xef9f0001;
code += 4;
}
case OP_SETFREG:
case OP_FMOVE:
+#ifdef ARM_FPU_FPA
ARM_MVFD (code, ins->dreg, ins->sreg1);
+#elif defined(ARM_FPU_VFP)
+ ARM_CPYD (code, ins->dreg, ins->sreg1);
+#endif
break;
case OP_FCONV_TO_R4:
+#ifdef ARM_FPU_FPA
ARM_MVFS (code, ins->dreg, ins->sreg1);
+#elif defined(ARM_FPU_VFP)
+ ARM_CVTD (code, ins->dreg, ins->sreg1);
+ ARM_CVTS (code, ins->dreg, ins->dreg);
+#endif
break;
- case CEE_JMP:
+ case OP_JMP:
/*
* Keep in sync with mono_arch_emit_epilog
*/
ARM_B (code, 0);
*(gpointer*)code = NULL;
code += 4;
- ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
- ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
+ code = emit_call_reg (code, ARMREG_IP);
} else {
ARM_BL (code, 0);
}
case OP_VCALL_REG:
case OP_VOIDCALL_REG:
case OP_CALL_REG:
- ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
- ARM_MOV_REG_REG (code, ARMREG_PC, ins->sreg1);
+ code = emit_call_reg (code, ins->sreg1);
break;
case OP_FCALL_MEMBASE:
case OP_LCALL_MEMBASE:
g_assert_not_reached ();
ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_LR);
break;
- case CEE_THROW: {
+ case OP_THROW: {
if (ins->sreg1 != ARMREG_R0)
ARM_MOV_REG_REG (code, ARMREG_R0, ins->sreg1);
mono_add_patch_info (cfg, code - cfg->native_code, MONO_PATCH_INFO_INTERNAL_METHOD,
ARM_B (code, 0);
*(gpointer*)code = NULL;
code += 4;
- ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
- ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
+ code = emit_call_reg (code, ARMREG_IP);
} else {
ARM_BL (code, 0);
}
ARM_B (code, 0);
*(gpointer*)code = NULL;
code += 4;
- ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
- ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
+ code = emit_call_reg (code, ARMREG_IP);
} else {
ARM_BL (code, 0);
}
}
ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
break;
- case CEE_ENDFINALLY:
+ case OP_ENDFINALLY:
if (arm_is_imm12 (ins->inst_left->inst_offset)) {
ARM_LDR_IMM (code, ARMREG_IP, ins->inst_left->inst_basereg, ins->inst_left->inst_offset);
} else {
case OP_LABEL:
ins->inst_c0 = code - cfg->native_code;
break;
- case CEE_BR:
+ case OP_BR:
if (ins->flags & MONO_INST_BRLABEL) {
/*if (ins->inst_i0->inst_c0) {
ARM_B (code, 0);
break;
/* floating point opcodes */
+#ifdef ARM_FPU_FPA
case OP_R8CONST:
/* FIXME: we can optimize the imm load by dealing with part of
* the displacement in LDFD (aligning to 512).
case CEE_CONV_R8:
ARM_FLTD (code, ins->dreg, ins->sreg1);
break;
+#elif defined(ARM_FPU_VFP)
+ case OP_R8CONST:
+ /* FIXME: we can optimize the imm load by dealing with part of
+ * the displacement in LDFD (aligning to 512).
+ */
+ code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
+ ARM_FLDD (code, ins->dreg, ARMREG_LR, 0);
+ break;
+ case OP_R4CONST:
+ code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)ins->inst_p0);
+ ARM_FLDS (code, ins->dreg, ARMREG_LR, 0);
+ ARM_CVTS (code, ins->dreg, ins->dreg);
+ break;
+ case OP_STORER8_MEMBASE_REG:
+ g_assert (arm_is_fpimm8 (ins->inst_offset));
+ ARM_FSTD (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
+ break;
+ case OP_LOADR8_MEMBASE:
+ g_assert (arm_is_fpimm8 (ins->inst_offset));
+ ARM_FLDD (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
+ break;
+ case OP_STORER4_MEMBASE_REG:
+ g_assert (arm_is_fpimm8 (ins->inst_offset));
+ ARM_FSTS (code, ins->sreg1, ins->inst_destbasereg, ins->inst_offset);
+ break;
+ case OP_LOADR4_MEMBASE:
+ g_assert (arm_is_fpimm8 (ins->inst_offset));
+ ARM_FLDS (code, ins->dreg, ins->inst_basereg, ins->inst_offset);
+ break;
+ case CEE_CONV_R_UN: {
+ g_assert_not_reached ();
+ break;
+ }
+ case CEE_CONV_R4:
+ g_assert_not_reached ();
+ //ARM_FLTS (code, ins->dreg, ins->sreg1);
+ break;
+ case CEE_CONV_R8:
+ g_assert_not_reached ();
+ //ARM_FLTD (code, ins->dreg, ins->sreg1);
+ break;
+#endif
case OP_FCONV_TO_I1:
code = emit_float_to_int (cfg, code, ins->dreg, ins->sreg1, 1, TRUE);
break;
ARM_MOV_REG_REG (code, ins->dreg, ins->sreg1);
break;
}
+#ifdef ARM_FPU_FPA
case OP_FADD:
ARM_FPA_ADFD (code, ins->dreg, ins->sreg1, ins->sreg2);
break;
break;
case OP_FNEG:
ARM_MNFD (code, ins->dreg, ins->sreg1);
+ break;
+#elif defined(ARM_FPU_VFP)
+ case OP_FADD:
+ ARM_VFP_ADDD (code, ins->dreg, ins->sreg1, ins->sreg2);
+ break;
+ case OP_FSUB:
+ ARM_VFP_SUBD (code, ins->dreg, ins->sreg1, ins->sreg2);
+ break;
+ case OP_FMUL:
+ ARM_VFP_MULD (code, ins->dreg, ins->sreg1, ins->sreg2);
+ break;
+ case OP_FDIV:
+ ARM_VFP_DIVD (code, ins->dreg, ins->sreg1, ins->sreg2);
break;
+ case OP_FNEG:
+ ARM_NEGD (code, ins->dreg, ins->sreg1);
+ break;
+#endif
case OP_FREM:
/* emulated */
g_assert_not_reached ();
case OP_FCOMPARE:
/* each fp compare op needs to do its own */
g_assert_not_reached ();
- ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
+ //ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
break;
case OP_FCEQ:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg1, ins->sreg2);
+#endif
ARM_MOV_REG_IMM8_COND (code, ins->dreg, 0, ARMCOND_NE);
ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_EQ);
break;
case OP_FCLT:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg1, ins->sreg2);
+#endif
ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
break;
case OP_FCLT_UN:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg1, ins->sreg2);
+#endif
ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
break;
case OP_FCGT:
/* swapped */
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg2, ins->sreg1);
+#endif
ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
break;
case OP_FCGT_UN:
/* swapped */
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg2, ins->sreg1);
+#endif
ARM_MOV_REG_IMM8 (code, ins->dreg, 0);
ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_MI);
ARM_MOV_REG_IMM8_COND (code, ins->dreg, 1, ARMCOND_VS);
* V Unordered ARMCOND_VS
*/
case OP_FBEQ:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg1, ins->sreg2);
+#endif
EMIT_COND_BRANCH (ins, CEE_BEQ - CEE_BEQ);
break;
case OP_FBNE_UN:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg1, ins->sreg2);
+#endif
EMIT_COND_BRANCH (ins, CEE_BNE_UN - CEE_BEQ);
break;
case OP_FBLT:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg1, ins->sreg2);
+#endif
EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
break;
case OP_FBLT_UN:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg1, ins->sreg2);
+#endif
EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set */
break;
case OP_FBGT:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg2, ins->sreg1);
+#endif
EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set, swapped args */
break;
case OP_FBGT_UN:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg2, ins->sreg1);
+#endif
EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_MI); /* N set, swapped args */
break;
case OP_FBGE:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg1, ins->sreg2);
+#endif
EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS);
break;
case OP_FBGE_UN:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg1, ins->sreg2);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg1, ins->sreg2);
+#endif
EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE);
break;
case OP_FBLE:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg2, ins->sreg1);
+#endif
EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_CS); /* swapped */
break;
case OP_FBLE_UN:
+#ifdef ARM_FPU_FPA
ARM_FCMP (code, ARM_FPA_CMF, ins->sreg2, ins->sreg1);
+#elif defined(ARM_FPU_VFP)
+ ARM_CMPD (code, ins->sreg2, ins->sreg1);
+#endif
EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_VS); /* V set */
EMIT_COND_BRANCH_FLAGS (ins, ARMCOND_GE); /* swapped */
break;
- case CEE_CKFINITE: {
+ case OP_CKFINITE: {
/*ppc_stfd (code, ins->sreg1, -8, ppc_sp);
ppc_lwz (code, ppc_r11, -8, ppc_sp);
ppc_rlwinm (code, ppc_r11, ppc_r11, 0, 1, 31);
const unsigned char *target;
if (patch_info->type == MONO_PATCH_INFO_SWITCH) {
- gpointer *table = (gpointer *)patch_info->data.table->table;
gpointer *jt = (gpointer*)(ip + 8);
int i;
/* jt is the inlined jump table, 2 instructions after ip
max_offset += 6;
while (ins) {
- max_offset += ((guint8 *)arm_cpu_desc [ins->opcode])[MONO_INST_LEN];
+ max_offset += ((guint8 *)ins_get_spec (ins->opcode))[MONO_INST_LEN];
ins = ins->next;
}
}
}
for (i = 0; i < sig->param_count + sig->hasthis; ++i) {
ArgInfo *ainfo = cinfo->args + i;
- inst = cfg->varinfo [pos];
+ inst = cfg->args [pos];
if (cfg->verbose_level > 2)
g_print ("Saving argument %d (type: %d)\n", i, ainfo->regtype);
}
break;
}
+ } else if (ainfo->regtype == RegTypeBaseGen) {
+ g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
+ g_assert (arm_is_imm12 (inst->inst_offset));
+ ARM_LDR_IMM (code, ARMREG_LR, ARMREG_SP, (prev_sp_offset + ainfo->offset));
+ ARM_STR_IMM (code, ARMREG_LR, inst->inst_basereg, inst->inst_offset + 4);
+ ARM_STR_IMM (code, ARMREG_R3, inst->inst_basereg, inst->inst_offset);
} else if (ainfo->regtype == RegTypeBase) {
g_assert (arm_is_imm12 (prev_sp_offset + ainfo->offset));
switch (ainfo->size) {
ARM_B (code, 0);
*(gpointer*)code = NULL;
code += 4;
- ARM_MOV_REG_REG (code, ARMREG_LR, ARMREG_PC);
- ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP);
+ code = emit_call_reg (code, ARMREG_IP);
} else {
ARM_BL (code, 0);
}
/* *(lmf_addr) = r1 */
ARM_STR_IMM (code, ARMREG_R1, ARMREG_R0, G_STRUCT_OFFSET (MonoLMF, previous_lmf));
/* save method info */
- code = mono_arm_emit_load_imm (code, ARMREG_R2, method);
+ code = mono_arm_emit_load_imm (code, ARMREG_R2, GPOINTER_TO_INT (method));
ARM_STR_IMM (code, ARMREG_R2, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, method));
ARM_STR_IMM (code, ARMREG_SP, ARMREG_R1, G_STRUCT_OFFSET (MonoLMF, ebp));
/* save the current IP */
void
mono_arch_emit_epilog (MonoCompile *cfg)
{
- MonoJumpInfo *patch_info;
MonoMethod *method = cfg->method;
int pos, i, rot_amount;
int max_epilog_size = 16 + 20*4;
}
/*
- * Keep in sync with CEE_JMP
+ * Keep in sync with OP_JMP
*/
code = cfg->native_code + cfg->code_len;
code = mono_arm_emit_load_imm (code, ARMREG_IP, cfg->stack_usage);
ARM_ADD_REG_REG (code, ARMREG_SP, ARMREG_SP, ARMREG_IP);
}
+ /* FIXME: add v4 thumb interworking support */
ARM_POP_NWB (code, cfg->used_int_regs | ((1 << ARMREG_SP) | (1 << ARMREG_PC)));
}
if (strcmp (name, "ArrayTypeMismatchException") == 0)
return MONO_EXC_ARRAY_TYPE_MISMATCH;
g_error ("Unknown intrinsic exception %s\n", name);
+ return -1;
}
void
mono_arch_emit_exceptions (MonoCompile *cfg)
{
MonoJumpInfo *patch_info;
- int nthrows, i;
+ int i;
guint8 *code;
const guint8* exc_throw_pos [MONO_EXC_INTRINS_NUM] = {NULL};
guint8 exc_throw_found [MONO_EXC_INTRINS_NUM] = {0};
- guint32 code_size;
- int exc_count = 0;
int max_epilog_size = 50;
/* count the number of exception infos */
patch_info->data.name = "mono_arch_throw_exception_by_name";
patch_info->ip.i = code - cfg->native_code;
ARM_B (code, 0);
- *(gpointer*)code = ex_name;
+ *(gconstpointer*)code = ex_name;
code += 4;
break;
}
projects / mono.git / blobdiff