* inssel-s390x.brg: Fix reg: OP_LDADDR(OP_S390_LOADARG) register setting.

[mono.git] / mono / mini / inssel-s390x.brg

diff --git a/mono/mini/inssel-s390x.brg b/mono/mini/inssel-s390x.brg
index aae547761f36b19bfaa6b87727342b57ec5a504d..5233c46056cc34bb238d335350eb77b2c4ab67f7 100644 (file)
--- a/mono/mini/inssel-s390x.brg
+++ b/mono/mini/inssel-s390x.brg
@@ -451,9 +451,9 @@ stmt: OP_OUTARG_VT (reg) {
                        MONO_OUTPUT_VTR (s, size, start_reg, STK_BASE, soffset);
                } else {
 //printf("OP_OUTARG_VT(reg) 2\n");
+                       treg = mono_regstate_next_int (s->rs);
                        MONO_OUTPUT_VTS (s, size, STK_BASE, soffset, treg,
                                         state->left->tree->inst_offset);
-                       treg = mono_regstate_next_int (s->rs);
                        MONO_EMIT_NEW_BIALU_IMM (s, OP_ADD_IMM, treg, STK_BASE, 
                                                 s->stack_offset);
                }
@@ -675,7 +675,7 @@ reg: OP_LDADDR (OP_S390_LOADARG) {
 
        treg = mono_regstate_next_int (s->rs);
        MONO_EMIT_NEW_UNALU (s, OP_S390_BKCHAIN, treg, s->frame_reg);
-       MONO_EMIT_NEW_LOAD_MEMBASE (s, treg, treg, state->left->tree->inst_offset);
+       MONO_EMIT_LOAD_MEMBASE (s, tree, state->reg1, treg, state->left->tree->inst_offset);
 }
 
 reg: OP_LDADDR (OP_S390_ARGPTR) "2" {
@@ -735,9 +735,10 @@ base: CEE_LDOBJ (OP_S390_STKARG) "0" {
 }
 
 
+reg: OP_ATOMIC_ADD_NEW_I8 (base, reg),
 reg: OP_ATOMIC_ADD_NEW_I4 (base, reg),
+reg: OP_ATOMIC_ADD_I8 (base, reg),
 reg: OP_ATOMIC_ADD_I4 (base, reg) {
-       tree->opcode = tree->opcode;
        tree->inst_basereg = state->left->tree->inst_basereg; 
        tree->inst_offset = state->left->tree->inst_offset; 
        tree->dreg = state->reg1;
@@ -746,8 +747,8 @@ reg: OP_ATOMIC_ADD_I4 (base, reg) {
        mono_bblock_add_inst (s->cbb, tree);
 }
 
+reg: OP_ATOMIC_EXCHANGE_I8 (base, reg),
 reg: OP_ATOMIC_EXCHANGE_I4 (base, reg) {
-       tree->opcode = OP_ATOMIC_EXCHANGE_I4;
        tree->dreg = state->reg1;
        tree->sreg2 = state->right->reg1;
        tree->inst_basereg = state->left->tree->inst_basereg;