#define MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_REG(cfg,basereg,offset,operand) do { \
MonoInst *inst; \
- inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
- inst->opcode = OP_AMD64_ICOMPARE_MEMBASE_REG; \
+ MONO_INST_NEW ((cfg), inst, OP_AMD64_ICOMPARE_MEMBASE_REG); \
inst->inst_basereg = basereg; \
inst->inst_offset = offset; \
inst->sreg2 = operand; \
#define MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_IMM(cfg,basereg,offset,operand) do { \
MonoInst *inst; \
- inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
- inst->opcode = OP_AMD64_ICOMPARE_MEMBASE_IMM; \
+ MONO_INST_NEW ((cfg), inst, OP_AMD64_ICOMPARE_MEMBASE_IMM); \
inst->inst_basereg = basereg; \
inst->inst_offset = offset; \
inst->inst_imm = operand; \
} \
} while (0)
-int cbranch_to_fcbranch (int opcode);
-int bialu_to_bialu_imm (int opcode);
-int ceq_to_fceq (int opcode);
-int call_reg_to_call_membase (int opcode);
-
%%
#
# (C) 2002 Ximian, Inc.
#
-stmt: OP_START_HANDLER {
- MonoInst *spvar = mono_find_spvar_for_region (s, s->cbb->region);
- MONO_EMIT_NEW_STORE_MEMBASE (s, OP_STORE_MEMBASE_REG, spvar->inst_basereg, spvar->inst_offset, X86_ESP);
+reg: CEE_LDIND_I8 (OP_REGVAR) {
+ state->reg1 = state->left->tree->dreg;
+}
+
+stmt: CEE_STIND_I8 (OP_REGVAR, reg) {
+ MONO_EMIT_NEW_UNALU (s, OP_MOVE, state->left->tree->dreg, state->right->reg1);
}
-stmt: CEE_ENDFINALLY {
- MonoInst *spvar = mono_find_spvar_for_region (s, s->cbb->region);
- MONO_EMIT_NEW_LOAD_MEMBASE (s, X86_ESP, spvar->inst_basereg, spvar->inst_offset);
- tree->opcode = CEE_RET;
+reg: CEE_LDIND_I1 (OP_REGVAR) {
+ MONO_EMIT_UNALU (s, tree, OP_SEXT_I1, state->reg1, state->left->tree->dreg);}
+
+reg: CEE_LDIND_I2 (OP_REGVAR) {
+ MONO_EMIT_UNALU (s, tree, OP_SEXT_I2, state->reg1, state->left->tree->dreg);}
+
+stmt: OP_START_HANDLER,
+stmt: OP_ENDFINALLY {
mono_bblock_add_inst (s->cbb, tree);
}
stmt: OP_ENDFILTER (reg) {
- MonoInst *spvar = mono_find_spvar_for_region (s, s->cbb->region);
- MONO_EMIT_NEW_UNALU (s, OP_MOVE, X86_EAX, state->left->reg1);
- MONO_EMIT_NEW_LOAD_MEMBASE (s, X86_ESP, spvar->inst_basereg, spvar->inst_offset);
- tree->opcode = CEE_RET;
+ tree->sreg1 = state->left->reg1;
mono_bblock_add_inst (s->cbb, tree);
}
+freg: OP_LCONV_TO_R_UN (reg),
freg: OP_LCONV_TO_R8 (reg) {
tree->sreg1 = state->left->reg1;
tree->dreg = state->reg1;
mono_bblock_add_inst (s->cbb, tree);
} else {
guint32 size = state->left->tree->inst_c0;
- size = (size + (MONO_ARCH_FRAME_ALIGNMENT - 1)) & ~ (MONO_ARCH_FRAME_ALIGNMENT - 1);
+ size = (size + (MONO_ARCH_LOCALLOC_ALIGNMENT - 1)) & ~ (MONO_ARCH_LOCALLOC_ALIGNMENT - 1);
MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, size);
MONO_EMIT_UNALU (s, tree, OP_MOVE, state->reg1, X86_ESP);
}
}
stmt: OP_OUTARG_REG (reg) {
- MonoCallInst *call = (MonoCallInst*)tree->inst_right;
+ MonoCallInst *call = tree->inst_call;
tree->opcode = OP_MOVE;
tree->sreg1 = state->left->reg1;
tree->dreg = mono_regstate_next_int (s->rs);
mono_bblock_add_inst (s->cbb, tree);
- mono_call_inst_add_outarg_reg (call, tree->dreg, tree->unused, FALSE);
+ mono_call_inst_add_outarg_reg (s, call, tree->dreg, tree->backend.reg3, FALSE);
}
# we need to reduce this code duplication with some burg syntax extension
}
stmt: OP_AMD64_OUTARG_XMMREG_R4 (freg) {
- MonoCallInst *call = (MonoCallInst*)tree->inst_right;
+ MonoCallInst *call = tree->inst_call;
tree->opcode = OP_AMD64_SET_XMMREG_R4;
tree->sreg1 = state->left->reg1;
tree->dreg = mono_regstate_next_float (s->rs);
mono_bblock_add_inst (s->cbb, tree);
- mono_call_inst_add_outarg_reg (call, tree->dreg, tree->unused, TRUE);
+ mono_call_inst_add_outarg_reg (s, call, tree->dreg, tree->backend.reg3, TRUE);
}
stmt: OP_AMD64_OUTARG_XMMREG_R8 (freg) {
- MonoCallInst *call = (MonoCallInst*)tree->inst_right;
+ MonoCallInst *call = tree->inst_call;
tree->opcode = OP_AMD64_SET_XMMREG_R8;
tree->sreg1 = state->left->reg1;
tree->dreg = mono_regstate_next_float (s->rs);
mono_bblock_add_inst (s->cbb, tree);
- mono_call_inst_add_outarg_reg (call, tree->dreg, tree->unused, TRUE);
+ mono_call_inst_add_outarg_reg (s, call, tree->dreg, tree->backend.reg3, TRUE);
}
stmt: OP_OUTARG_VT (CEE_LDOBJ (base)) {
stmt: OP_OUTARG_VT (reg) {
tree->opcode = OP_X86_PUSH;
- tree->sreg1 = state->left->tree->dreg;
+ tree->sreg1 = state->left->reg1;
mono_bblock_add_inst (s->cbb, tree);
}
stmt: OP_AMD64_OUTARG_ALIGN_STACK {
- MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
+ MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, tree->inst_c0);
+}
+
+stmt: OP_AMD64_SAVE_SP_TO_LMF {
+ mono_bblock_add_inst (s->cbb, tree);
}
base: OP_INARG_VT (base) {
tree->sreg1 = state->left->reg1;
tree->sreg2 = reg;
tree->inst_imm = G_STRUCT_OFFSET (MonoArray, vector);
- tree->unused = fast_log2 [size];
+ tree->backend.shift_amount = fast_log2 [size];
mono_bblock_add_inst (s->cbb, tree);
} else {
int mult_reg = mono_regstate_next_int (s->rs);
reg: CEE_ADD(reg, CEE_LDIND_I4 (base)) {
MonoInst *base = state->right->left->tree;
- MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_ADD_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
+ MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_ADD_REG_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
}
reg: CEE_SUB(reg, CEE_LDIND_I4 (base)) {
MonoInst *base = state->right->left->tree;
- MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_SUB_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
+ MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_SUB_REG_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
}
reg: CEE_MUL(reg, CEE_LDIND_I4 (base)) {
MonoInst *base = state->right->left->tree;
- MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_MUL_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
+ MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_MUL_REG_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
}
reg: OP_LSHL (reg, reg),
reg: OP_LREM (reg, reg),
reg: OP_LREM_UN (reg, reg),
reg: OP_LMUL_OVF (reg, reg),
-reg: OP_LMUL_OVF_UN (reg, reg) "0" {
+reg: OP_LMUL_OVF_UN (reg, reg),
+reg: OP_IMIN (reg, reg),
+reg: OP_IMIN_UN (reg, reg),
+reg: OP_IMAX (reg, reg),
+reg: OP_IMAX_UN (reg, reg),
+reg: OP_LMIN (reg, reg),
+reg: OP_LMIN_UN (reg, reg),
+reg: OP_LMAX (reg, reg),
+reg: OP_LMAX_UN (reg, reg) "0" {
MONO_EMIT_BIALU (s, tree, tree->opcode, state->reg1, state->left->reg1, state->right->reg1);
}
mono_bblock_add_inst (s->cbb, tree);
}
+reg: OP_ATOMIC_CAS_IMM_I4 (base, reg) {
+ tree->opcode = tree->opcode;
+ tree->dreg = state->reg1;
+ tree->sreg2 = state->right->reg1;
+ tree->inst_basereg = state->left->tree->inst_basereg;
+ tree->inst_offset = state->left->tree->inst_offset;
+
+ mono_bblock_add_inst (s->cbb, tree);
+}
+
# Optimized call instructions
-# mono_arch_patch_delegate_trampoline depends on these
reg: OP_CALL_REG (CEE_LDIND_I (base)),
freg: OP_FCALL_REG (CEE_LDIND_I (base)),
reg: OP_LCALL_REG (CEE_LDIND_I (base)) {
%%
-int
+static int
bialu_to_bialu_imm (int opcode)
{
switch (opcode) {
return -1;
}
-int
+static int
cbranch_to_fcbranch (int opcode)
{
switch (opcode) {
return -1;
}
-int
+static int
ceq_to_fceq (int opcode)
{
switch (opcode) {
return -1;
}
-int
+static int
call_reg_to_call_membase (int opcode)
{
switch (opcode) {