#define MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_REG(cfg,basereg,offset,operand) do { \
MonoInst *inst; \
- inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
- inst->opcode = OP_AMD64_ICOMPARE_MEMBASE_REG; \
+ MONO_INST_NEW ((cfg), inst, OP_AMD64_ICOMPARE_MEMBASE_REG); \
inst->inst_basereg = basereg; \
inst->inst_offset = offset; \
inst->sreg2 = operand; \
#define MONO_EMIT_NEW_AMD64_ICOMPARE_MEMBASE_IMM(cfg,basereg,offset,operand) do { \
MonoInst *inst; \
- inst = mono_mempool_alloc0 ((cfg)->mempool, sizeof (MonoInst)); \
- inst->opcode = OP_AMD64_ICOMPARE_MEMBASE_IMM; \
+ MONO_INST_NEW ((cfg), inst, OP_AMD64_ICOMPARE_MEMBASE_IMM); \
inst->inst_basereg = basereg; \
inst->inst_offset = offset; \
inst->inst_imm = operand; \
mono_bblock_add_inst (s->cbb, tree);
}
+freg: OP_LCONV_TO_R_UN (reg),
freg: OP_LCONV_TO_R8 (reg) {
tree->sreg1 = state->left->reg1;
tree->dreg = state->reg1;
stmt: OP_OUTARG_VT (reg) {
tree->opcode = OP_X86_PUSH;
- tree->sreg1 = state->left->tree->dreg;
+ tree->sreg1 = state->left->reg1;
mono_bblock_add_inst (s->cbb, tree);
}
stmt: OP_AMD64_OUTARG_ALIGN_STACK {
- MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, 8);
+ MONO_EMIT_NEW_BIALU_IMM (s, OP_SUB_IMM, X86_ESP, X86_ESP, tree->inst_c0);
+}
+
+stmt: OP_AMD64_SAVE_SP_TO_LMF {
+ mono_bblock_add_inst (s->cbb, tree);
}
base: OP_INARG_VT (base) {
reg: CEE_ADD(reg, CEE_LDIND_I4 (base)) {
MonoInst *base = state->right->left->tree;
- MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_ADD_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
+ MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_ADD_REG_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
}
reg: CEE_SUB(reg, CEE_LDIND_I4 (base)) {
MonoInst *base = state->right->left->tree;
- MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_SUB_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
+ MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_SUB_REG_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
}
reg: CEE_MUL(reg, CEE_LDIND_I4 (base)) {
MonoInst *base = state->right->left->tree;
- MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_MUL_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
+ MONO_EMIT_BIALU_MEMBASE (cfg, tree, OP_X86_MUL_REG_MEMBASE, state->reg1, state->left->reg1, base->inst_basereg, base->inst_offset);
}
reg: OP_LSHL (reg, reg),
reg: OP_LMUL_OVF (reg, reg),
reg: OP_LMUL_OVF_UN (reg, reg),
reg: OP_IMIN (reg, reg),
+reg: OP_IMIN_UN (reg, reg),
reg: OP_IMAX (reg, reg),
+reg: OP_IMAX_UN (reg, reg),
reg: OP_LMIN (reg, reg),
-reg: OP_LMAX (reg, reg) "0" {
+reg: OP_LMIN_UN (reg, reg),
+reg: OP_LMAX (reg, reg),
+reg: OP_LMAX_UN (reg, reg) "0" {
MONO_EMIT_BIALU (s, tree, tree->opcode, state->reg1, state->left->reg1, state->right->reg1);
}
mono_bblock_add_inst (s->cbb, tree);
}
+reg: OP_ATOMIC_CAS_IMM_I4 (base, reg) {
+ tree->opcode = tree->opcode;
+ tree->dreg = state->reg1;
+ tree->sreg2 = state->right->reg1;
+ tree->inst_basereg = state->left->tree->inst_basereg;
+ tree->inst_offset = state->left->tree->inst_offset;
+
+ mono_bblock_add_inst (s->cbb, tree);
+}
+
# Optimized call instructions
-# mono_arch_patch_delegate_trampoline depends on these
reg: OP_CALL_REG (CEE_LDIND_I (base)),
freg: OP_FCALL_REG (CEE_LDIND_I (base)),
reg: OP_LCALL_REG (CEE_LDIND_I (base)) {