* cpu-x86.md: Added new instructions to handle float to int using SSE regs.

[mono.git] / mono / mini / cpu-x86.md

diff --git a/mono/mini/cpu-x86.md b/mono/mini/cpu-x86.md
index 6dde0fa18e52d399c4815c0767dd0bb62964b322..e3cb5afe52c7b4bb1d715d64cff92de1c15a07d7 100644 (file)
--- a/mono/mini/cpu-x86.md
+++ b/mono/mini/cpu-x86.md
@@ -21,6 +21,7 @@
 #      l  long reg (forced eax:edx)
 #      L  long reg (dynamic)
 #      y  the reg needs to be one of EAX,EBX,ECX,EDX (sete opcodes)
+#      x  XMM reg (XMM0 - X007)
 #
 # len:number         describe the maximun length in bytes of the instruction
 #                   number is a positive integer.  If the length is not specified
@@ -86,7 +87,9 @@ int_shl: dest:i src1:i src2:s clob:1 len:2
 int_shr: dest:i src1:i src2:s clob:1 len:2
 int_shr_un: dest:i src1:i src2:s clob:1 len:2
 int_min: dest:i src1:i src2:i len:16 clob:1
+int_min_un: dest:i src1:i src2:i len:16 clob:1
 int_max: dest:i src1:i src2:i len:16 clob:1
+int_max_un: dest:i src1:i src2:i len:16 clob:1
 
 int_neg: dest:i src1:i len:2 clob:1
 int_not: dest:i src1:i len:2 clob:1
@@ -124,13 +127,13 @@ outarg: src1:i len:1
 outarg_imm: len:5
 setret: dest:a src1:i len:2
 setlret: dest:l src1:i src2:i len:4
-checkthis: src1:b len:2
+checkthis: src1:b len:3
 voidcall: len:17 clob:c
 voidcall_reg: src1:i len:11 clob:c
 voidcall_membase: src1:b len:16 clob:c
-fcall: dest:f len:17 clob:c
-fcall_reg: dest:f src1:i len:11 clob:c
-fcall_membase: dest:f src1:b len:16 clob:c
+fcall: dest:f len:48 clob:c
+fcall_reg: dest:f src1:i len:48 clob:c
+fcall_membase: dest:f src1:b len:48 clob:c
 lcall: dest:l len:17 clob:c
 lcall_reg: dest:l src1:i len:11 clob:c
 lcall_membase: dest:l src1:b len:16 clob:c
@@ -302,6 +305,144 @@ sext_i2: dest:i src1:y len:3
 tls_get: dest:i len:20
 atomic_add_i4: src1:b src2:i dest:i len:16
 atomic_add_new_i4: src1:b src2:i dest:i len:16
-atomic_exchange_i4: src1:b src2:i dest:i len:24
+atomic_exchange_i4: src1:b src2:i dest:a len:24
+atomic_cas_imm_i4: src1:b src2:i dest:a len:24
 memory_barrier: len:16
 
+relaxed_nop: len:2
+
+# Linear IR opcodes
+nop: len:0
+dummy_use: len:0
+dummy_store: len:0
+not_reached: len:0
+not_null: src1:i len:0
+
+jump_table: dest:i len:5
+
+int_adc: dest:i src1:i src2:i len:2 clob:1
+int_addcc: dest:i src1:i src2:i len:2 clob:1
+int_subcc: dest:i src1:i src2:i len:2 clob:1
+int_sbb: dest:i src1:i src2:i len:2 clob:1
+
+int_add_imm: dest:i src1:i len:6 clob:1
+int_sub_imm: dest:i src1:i len:6 clob:1
+int_mul_imm: dest:i src1:i len:9
+int_div_imm: dest:a src1:a len:15 clob:d
+int_div_un_imm: dest:a src1:a len:15 clob:d
+int_rem_imm: dest:a src1:a len:15 clob:d
+int_rem_un_imm: dest:d src1:a len:15 clob:a
+int_and_imm: dest:i src1:i len:6 clob:1
+int_or_imm: dest:i src1:i len:6 clob:1
+int_xor_imm: dest:i src1:i len:6 clob:1
+int_shl_imm: dest:i src1:i len:6 clob:1
+int_shr_imm: dest:i src1:i len:6 clob:1
+int_shr_un_imm: dest:i src1:i len:6 clob:1
+
+int_conv_to_r_un: dest:f src1:i len:32
+
+int_ceq: dest:y len:6
+int_cgt: dest:y len:6
+int_cgt_un: dest:y len:6
+int_clt: dest:y len:6
+int_clt_un: dest:y len:6
+
+cond_exc_ieq: len:6
+cond_exc_ine_un: len:6
+cond_exc_ilt: len:6
+cond_exc_ilt_un: len:6
+cond_exc_igt: len:6
+cond_exc_igt_un: len:6
+cond_exc_ige: len:6
+cond_exc_ige_un: len:6
+cond_exc_ile: len:6
+cond_exc_ile_un: len:6
+cond_exc_iov: len:6
+cond_exc_ino: len:6
+cond_exc_ic: len:6
+cond_exc_inc: len:6
+
+icompare: src1:i src2:i len:2
+icompare_imm: src1:i len:6
+
+cmov_ieq: dest:i src1:i src2:i len:16 clob:1
+cmov_ige: dest:i src1:i src2:i len:16 clob:1
+cmov_igt: dest:i src1:i src2:i len:16 clob:1
+cmov_ile: dest:i src1:i src2:i len:16 clob:1
+cmov_ilt: dest:i src1:i src2:i len:16 clob:1
+cmov_ine_un: dest:i src1:i src2:i len:16 clob:1
+cmov_ige_un: dest:i src1:i src2:i len:16 clob:1
+cmov_igt_un: dest:i src1:i src2:i len:16 clob:1
+cmov_ile_un: dest:i src1:i src2:i len:16 clob:1
+cmov_ilt_un: dest:i src1:i src2:i len:16 clob:1
+
+long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:30
+long_conv_to_r8_2: dest:f src1:i src2:i len:37 
+long_conv_to_r4_2: dest:f src1:i src2:i len:64
+long_conv_to_r_un_2: dest:f src1:i src2:i len:37 
+
+fmove: dest:f src1:f
+float_conv_to_r4: dest:f src1:f
+
+load_mem: dest:i len:9
+loadi4_mem: dest:i len:9
+loadu1_mem: dest:i len:9
+loadu2_mem: dest:i len:9
+
+vcall2: len:17 clob:c
+vcall2_reg: src1:i len:11 clob:c
+vcall2_membase: src1:b len:16 clob:c
+
+localloc_imm: dest:i len:120
+
+x86_add_membase_reg: src1:b src2:i len:11
+x86_sub_membase_reg: src1:b src2:i len:11
+x86_and_membase_reg: src1:b src2:i len:11
+x86_or_membase_reg: src1:b src2:i len:11
+x86_xor_membase_reg: src1:b src2:i len:11
+x86_mul_membase_reg: src1:b src2:i len:13
+
+x86_and_reg_membase: dest:i src1:i src2:b clob:1 len:6
+x86_or_reg_membase: dest:i src1:i src2:b clob:1 len:6
+x86_xor_reg_membase: dest:i src1:i src2:b clob:1 len:6
+
+x86_fxch: len:2
+
+addps: dest:x src1:x src2:x len:3 clob:1
+divps: dest:x src1:x src2:x len:3 clob:1
+mulps: dest:x src1:x src2:x len:3 clob:1
+subps: dest:x src1:x src2:x len:3 clob:1
+maxps: dest:x src1:x src2:x len:3 clob:1
+minps: dest:x src1:x src2:x len:3 clob:1
+
+haddps: dest:x src1:x src2:x len:4 clob:1
+hsubps: dest:x src1:x src2:x len:4 clob:1
+addsubps: dest:x src1:x src2:x len:4 clob:1
+
+pand: dest:x src1:x src2:x len:4 clob:1
+por: dest:x src1:x src2:x len:4 clob:1
+pxor: dest:x src1:x src2:x len:4 clob:1
+
+sqrtps: dest:x src1:x len:4
+rsqrtps: dest:x src1:x len:4
+shuffleps: dest:x src1:x len:5
+
+xmove: dest:x src1:x len:4
+xzero: dest:x len:4
+
+extract_i4: dest:i src1:x len:4
+iconv_to_r8_raw: dest:f src1:i len:17 
+
+loadx_membase: dest:x src1:b len:7
+storex_membase: dest:b src1:x len:7
+storex_membase_reg: dest:b src1:x len:7
+
+loadx_aligned_membase: dest:x src1:b len:7
+storex_aligned_membase_reg: dest:b src1:x len:7
+
+push_r4: src1:f len:13
+loadx_stack: dest:x len: 13
+
+fconv_to_r8_x: dest:x src1:f len:60 
+xconv_r8_to_i4: dest:y src1:x len:60
+