This commit was manufactured by cvs2svn to create branch 'mono-1-0'.

[mono.git] / mono / mini / cpu-pentium.md

diff --git a/mono/mini/cpu-pentium.md b/mono/mini/cpu-pentium.md
index adebcb94ae424b499eca4a813996ebc7ffa3f4bc..2568eac81f65247c9c973e833a100cb1c9d1ed7b 100644 (file)
--- a/mono/mini/cpu-pentium.md
+++ b/mono/mini/cpu-pentium.md
@@ -17,9 +17,15 @@
 #      f  floating point register
 #      a  EAX register
 #       d  EDX register
+#      l  long reg (forced eax:edx)
+#              L  long reg (dynamic)
 #
 # len:number         describe the maximun length in bytes of the instruction
-# number is a positive integer
+#                   number is a positive integer.  If the length is not specified
+#                    it defaults to zero.   But lengths are only checked if the given opcode 
+#                    is encountered during compilation. Some opcodes, like CONV_U4 are 
+#                    transformed into other opcodes in the brg files, so they do not show up 
+#                    during code generation.
 #
 # cost:number        describe how many cycles are needed to complete the instruction (unused)
 #
@@ -29,8 +35,8 @@
 #      c  clobbers caller-save registers
 #      1  clobbers the first source register
 #      a  EAX is clobbered
-#       d  EAX and EDX are clobbered
-#      s  the src1 operand needs to be in ECX (shift opcodes)
+#   d  EAX and EDX are clobbered
+#      s  the src2 operand needs to be in ECX (shift opcodes)
 #      x  both the source operands are clobbered (xchg)
 #
 # flags:spec        describe if the instruction uses or sets the flags (unused)
@@ -303,22 +309,17 @@ checkthis: src1:b len:3
 voidcall: len:11 clob:c
 voidcall_reg: src1:i len:11 clob:c
 voidcall_membase: src1:b len:16 clob:c
-voidcall_imm: len:11 clob:c
 fcall: dest:f len:11 clob:c
 fcall_reg: dest:f src1:i len:11 clob:c
 fcall_membase: dest:f src1:b len:16 clob:c
-fcall_imm: dest:f len:11 clob:c
 lcall: dest:l len:11 clob:c
 lcall_reg: dest:l src1:i len:11 clob:c
 lcall_membase: dest:l src1:b len:16 clob:c
-lcall_imm: dest:l len:16 clob:c
 vcall: len:11 clob:c
 vcall_reg: src1:i len:11 clob:c
 vcall_membase: src1:b len:16 clob:c
-vcall_imm: len:16 clob:c
 call_reg: dest:a src1:i len:11 clob:c
 call_membase: dest:a src1:b len:16 clob:c
-call_imm: dest:a len:16 clob:c
 trap:
 iconst: dest:i len:5
 i8const:
@@ -393,9 +394,9 @@ long_rem_un:
 long_and:
 long_or:
 long_xor:
-long_shl:
-long_shr:
-long_shr_un:
+long_shl: dest:L src1:L src2:i clob:s len:21
+long_shr: dest:L src1:L src2:i clob:s len:22
+long_shr_un: dest:L src1:L src2:i clob:s len:22
 long_neg:
 long_not:
 long_conv_to_i1:
@@ -442,9 +443,9 @@ long_clt:
 long_clt_un:
 long_conv_to_r_un: dest:f src1:i src2:i len:37 
 long_conv_to_u:
-long_shr_imm:
-long_shr_un_imm:
-long_shl_imm:
+long_shr_imm: dest:L src1:L len:10
+long_shr_un_imm: dest:L src1:L len:10
+long_shl_imm: dest:L src1:L len:10
 long_add_imm:
 long_sub_imm:
 long_beq:
@@ -458,32 +459,32 @@ long_bge_un:
 long_ble:
 long_ble_un:
 float_beq: len:12
-float_bne_un: len:12
+float_bne_un: len:18
 float_blt: len:12
 float_blt_un: len:20
 float_bgt: len:12
 float_btg_un: len:20
-float_bge: len:12
+float_bge: len:22
 float_bge_un: len:12
-float_ble: len:12
+float_ble: len:22
 float_ble_un: len:12
-float_add: src1:f src2:f len:2
-float_sub: src1:f src2:f len:2
-float_mul: src1:f src2:f len:2
-float_div: src1:f src2:f len:2
-float_div_un: src1:f src2:f len:2
-float_rem: src1:f src2:f len:17
-float_rem_un: src1:f src2:f len:17
+float_add: dest:f src1:f src2:f len:2
+float_sub: dest:f src1:f src2:f len:2
+float_mul: dest:f src1:f src2:f len:2
+float_div: dest:f src1:f src2:f len:2
+float_div_un: dest:f src1:f src2:f len:2
+float_rem: dest:f src1:f src2:f len:17
+float_rem_un: dest:f src1:f src2:f len:17
 float_neg: dest:f src1:f len:2
 float_not: dest:f src1:f len:2
 float_conv_to_i1: dest:i src1:f len:39
 float_conv_to_i2: dest:i src1:f len:39
 float_conv_to_i4: dest:i src1:f len:39
-float_conv_to_i8: dest:l src1:f len:39
+float_conv_to_i8: dest:L src1:f len:39
 float_conv_to_r4:
 float_conv_to_r8:
 float_conv_to_u4: dest:i src1:f len:39
-float_conv_to_u8: dest:l src1:f len:39
+float_conv_to_u8: dest:L src1:f len:39
 float_conv_to_u2: dest:i src1:f len:39
 float_conv_to_u1: dest:i src1:f len:39
 float_conv_to_i: dest:i src1:f len:39
@@ -542,6 +543,9 @@ x86_fpop: src1:f len:2
 x86_fp_load_i8: dest:f src1:b len:7
 x86_fp_load_i4: dest:f src1:b len:7
 x86_seteq_membase: src1:b len:7
+x86_add_membase: dest:i src1:i src2:b clob:1 len:11
+x86_sub_membase: dest:i src1:i src2:b clob:1 len:11
+x86_mul_membase: dest:i src1:i src2:b clob:1 len:13
 adc: dest:i src1:i src2:i len:2 clob:1
 addcc: dest:i src1:i src2:i len:2 clob:1
 subcc: dest:i src1:i src2:i len:2 clob:1
@@ -549,11 +553,11 @@ adc_imm: dest:i src1:i len:6 clob:1
 sbb: dest:i src1:i src2:i len:2 clob:1
 sbb_imm: dest:i src1:i len:6 clob:1
 br_reg: src1:i len:2
-sin: dest:f src1:f len:2
-cos: dest:f src1:f len:2
+sin: dest:f src1:f len:6
+cos: dest:f src1:f len:6
 abs: dest:f src1:f len:2
-tan: dest:f src1:f len:45
-atan: dest:f src1:f len:4
+tan: dest:f src1:f len:49
+atan: dest:f src1:f len:8
 sqrt: dest:f src1:f len:2
 op_bigmul: len:2 dest:l src1:a src2:i
 op_bigmul_un: len:2 dest:l src1:a src2:i