Mon Jan 19 17:44:50 CET 2004 Paolo Molaro <lupus@ximian.com>

[mono.git] / mono / mini / cpu-pentium.md

diff --git a/mono/mini/cpu-pentium.md b/mono/mini/cpu-pentium.md
index dbcf094bdec8a1ff188a6d40ae6255b09599e91f..216537787a49902ef42b635ab1dd3d4f0b5275b3 100644 (file)
--- a/mono/mini/cpu-pentium.md
+++ b/mono/mini/cpu-pentium.md
@@ -134,8 +134,8 @@ stind.i1: src1:b src2:i
 stind.i2: src1:b src2:i
 stind.i4: src1:b src2:i
 stind.i8:
-stind.r4: src1:b src2:f
-stind.r8: src1:b src2:f
+stind.r4: dest:f src1:b
+stind.r8: dest:f src1:b
 add: dest:i src1:i src2:i len:2 clob:1
 sub: dest:i src1:i src2:i len:2 clob:1
 mul: dest:i src1:i src2:i len:3 clob:1
@@ -230,7 +230,7 @@ add.ovf:
 add.ovf.un:
 mul.ovf: dest:i src1:i src2:i clob:1 len:9
 # this opcode is handled specially in the code generator
-mul.ovf.un: dest:i src1:i src2:i len:12
+mul.ovf.un: dest:i src1:i src2:i len:16
 sub.ovf:
 sub.ovf.un:
 endfinally:
@@ -260,7 +260,7 @@ starg:
 ldloc:
 ldloca:
 stloc:
-localloc: dest:i src1:i len:32
+localloc: dest:i src1:i len:64
 endfilter:
 unaligned.:
 volatile.:
@@ -301,19 +301,19 @@ setret: dest:a src1:i len:2
 setlret: dest:l src1:i src2:i len:4
 checkthis: src1:b len:3
 voidcall: len:11 clob:c
-voidcall_reg: src1:i len:5 clob:c
-voidcall_membase: src1:b len:10 clob:c
-fcall: dest:f len:8 clob:c
-fcall_reg: dest:f src1:i len:5 clob:c
-fcall_membase: dest:f src1:b len:10 clob:c
-lcall: dest:l len:8 clob:c
-lcall_reg: dest:l src1:i len:5 clob:c
-lcall_membase: dest:l src1:b len:10 clob:c
-vcall: len:8 clob:c
-vcall_reg: src1:i len:5 clob:c
-vcall_membase: src1:b len:10 clob:c
-call_reg: dest:a src1:i len:5 clob:c
-call_membase: dest:a src1:b len:10 clob:c
+voidcall_reg: src1:i len:11 clob:c
+voidcall_membase: src1:b len:16 clob:c
+fcall: dest:f len:11 clob:c
+fcall_reg: dest:f src1:i len:11 clob:c
+fcall_membase: dest:f src1:b len:16 clob:c
+lcall: dest:l len:11 clob:c
+lcall_reg: dest:l src1:i len:11 clob:c
+lcall_membase: dest:l src1:b len:16 clob:c
+vcall: len:11 clob:c
+vcall_reg: src1:i len:11 clob:c
+vcall_membase: src1:b len:16 clob:c
+call_reg: dest:a src1:i len:11 clob:c
+call_membase: dest:a src1:b len:16 clob:c
 trap:
 iconst: dest:i len:5
 i8const:
@@ -345,6 +345,7 @@ loadu4_membase: dest:i src1:b len:6
 loadi8_membase: dest:i src1:b
 loadr4_membase: dest:f src1:b len:6
 loadr8_membase: dest:f src1:b len:6
+loadr8_spill_membase: src1:b len:8
 loadu4_mem: dest:i len:9
 move: dest:i src1:i len:2
 add_imm: dest:i src1:i len:6 clob:1
@@ -461,13 +462,13 @@ float_bge: len:12
 float_bge_un: len:12
 float_ble: len:12
 float_ble_un: len:12
-float_add: len:2
-float_sub: len:2
-float_mul: len:2
-float_div: len:2
-float_div_un: len:2
-float_rem: len:17
-float_rem_un: len:17
+float_add: src1:f src2:f len:2
+float_sub: src1:f src2:f len:2
+float_mul: src1:f src2:f len:2
+float_div: src1:f src2:f len:2
+float_div_un: src1:f src2:f len:2
+float_rem: src1:f src2:f len:17
+float_rem_un: src1:f src2:f len:17
 float_neg: dest:f src1:f len:2
 float_not: dest:f src1:f len:2
 float_conv_to_i1: dest:i src1:f len:39
@@ -485,7 +486,7 @@ float_conv_to_ovf_i: dest:a src1:f len:30
 float_conv_to_ovd_u: dest:a src1:f len:30
 float_add_ovf:
 float_add_ovf_un:
-float_mul_ovf:
+float_mul_ovf: 
 float_mul_ovf_un:
 float_sub_ovf:
 float_sub_ovf_un: