2006-01-03 Zoltan Varga <vargaz@gmail.com>

[mono.git] / mono / mini / cpu-g4.md

diff --git a/mono/mini/cpu-g4.md b/mono/mini/cpu-g4.md
index 2e69b5278d98137126dbf19d4451d7f368355b40..ac4e5b1ed2af78bb1376e088d172cf6ad71ad159 100644 (file)
--- a/mono/mini/cpu-g4.md
+++ b/mono/mini/cpu-g4.md
@@ -13,6 +13,7 @@
 #
 # register may have the following values:
 #      i  integer register
+#      a  r3 register (output from calls)
 #      b  base register (used in address references)
 #      f  floating point register
 #
@@ -44,6 +45,7 @@
 #
 # See the code in mini-x86.c for more details on how the specifiers are used.
 #
+memory_barrier: len:4
 nop: len:4
 break: len:4
 ldarg.0:
@@ -80,11 +82,10 @@ ldc.i4:
 ldc.i8:
 ldc.r4:
 ldc.r8:
-unused99:
 dup:
 pop:
-jmp:
-call: dest:a clob:c len:4
+jmp: len:92
+call: dest:a clob:c len:16
 calli:
 ret:
 br.s:
@@ -135,10 +136,10 @@ stind.r8: src1:b src2:f
 add: dest:i src1:i src2:i len:4
 sub: dest:i src1:i src2:i len:4
 mul: dest:i src1:i src2:i len:4
-div: dest:a src1:i src2:i len:4
-div.un: dest:a src1:i src2:i len:4
-rem: dest:d src1:i src2:i len:12
-rem.un: dest:d src1:i src2:i len:12
+div: dest:i src1:i src2:i len:40
+div.un: dest:i src1:i src2:i len:16
+rem: dest:i src1:i src2:i len:48
+rem.un: dest:i src1:i src2:i len:24
 and: dest:i src1:i src2:i len:4
 or: dest:i src1:i src2:i len:4
 xor: dest:i src1:i src2:i len:4
@@ -151,8 +152,8 @@ conv.i1: dest:i src1:i len:4
 conv.i2: dest:i src1:i len:4
 conv.i4: dest:i src1:i len:4
 conv.i8:
-conv.r4: dest:f src1:i len:7
-conv.r8: dest:f src1:i len:7
+conv.r4: dest:f src1:i len:36
+conv.r8: dest:f src1:i len:36
 conv.u4: dest:i src1:i
 conv.u8:
 callvirt:
@@ -162,11 +163,10 @@ ldstr:
 newobj:
 castclass:
 isinst:
-conv.r.un:
-unused58:
-unused1:
+conv.r.un: dest:f src1:i len:32
 unbox:
-throw: src1:i len:8
+throw: src1:i len:20
+op_rethrow: src1:i len:20
 ldfld:
 ldflda:
 stfld:
@@ -207,22 +207,6 @@ stelem.i8:
 stelem.r4:
 stelem.r8:
 stelem.ref:
-unused2:
-unused3:
-unused4:
-unused5:
-unused6:
-unused7:
-unused8:
-unused9:
-unused10:
-unused11:
-unused12:
-unused13:
-unused14:
-unused15:
-unused16:
-unused17:
 conv.ovf.i1:
 conv.ovf.u1:
 conv.ovf.i2:
@@ -231,68 +215,32 @@ conv.ovf.i4:
 conv.ovf.u4:
 conv.ovf.i8:
 conv.ovf.u8:
-unused50:
-unused18:
-unused19:
-unused20:
-unused21:
-unused22:
-unused23:
 refanyval:
-ckfinite: dest:f src1:f len:22
-unused24:
-unused25:
+ckfinite: dest:f src1:f len:24
 mkrefany:
-unused59:
-unused60:
-unused61:
-unused62:
-unused63:
-unused64:
-unused65:
-unused66:
-unused67:
 ldtoken:
 conv.u2: dest:i src1:i len:4
 conv.u1: dest:i src1:i len:4
 conv.i: dest:i src1:i len:4
 conv.ovf.i:
 conv.ovf.u:
-add.ovf:
-add.ovf.un:
-mul.ovf: dest:i src1:i src2:i len:8
+add.ovf: dest:i src1:i src2:i len:16
+add.ovf.un: dest:i src1:i src2:i len:16
+mul.ovf: dest:i src1:i src2:i len:16
 # this opcode is handled specially in the code generator
-mul.ovf.un: dest:i src1:i src2:i len:12
-sub.ovf:
-sub.ovf.un:
-endfinally: len:10
+mul.ovf.un: dest:i src1:i src2:i len:16
+sub.ovf: dest:i src1:i src2:i len:16
+sub.ovf.un: dest:i src1:i src2:i len:16
+add_ovf_carry: dest:i src1:i src2:i len:16
+sub_ovf_carry: dest:i src1:i src2:i len:16
+add_ovf_un_carry: dest:i src1:i src2:i len:16
+sub_ovf_un_carry: dest:i src1:i src2:i len:16
+start_handler: len:8
+endfinally: len:12
 leave:
 leave.s:
 stind.i:
 conv.u: dest:i src1:i len:4
-unused26:
-unused27:
-unused28:
-unused29:
-unused30:
-unused31:
-unused32:
-unused33:
-unused34:
-unused35:
-unused36:
-unused37:
-unused38:
-unused39:
-unused40:
-unused41:
-unused42:
-unused43:
-unused44:
-unused45:
-unused46:
-unused47:
-unused48:
 prefix7:
 prefix6:
 prefix5:
@@ -309,39 +257,25 @@ clt: dest:i len:12
 clt.un: dest:i len:12
 ldftn:
 ldvirtftn:
-unused56:
 ldarg:
 ldarga:
 starg:
 ldloc:
 ldloca:
 stloc:
-localloc: dest:i src1:i len:30
-unused57:
-endfilter:
+localloc: dest:i src1:i len:60
+endfilter: len:12
 unaligned.:
 volatile.:
 tail.:
 initobj:
-unused68:
 cpblk:
 initblk:
-unused69:
 rethrow:
-unused:
 sizeof:
 refanytype:
-unused52:
-unused53:
-unused54:
-unused55:
-unused70:
 illegal:
 endmac:
-mono_func1:
-mono_proc2:
-mono_proc3:
-mono_free:
 mono_objaddr:
 mono_ldptr:
 mono_vtaddr:
@@ -358,50 +292,51 @@ fcompare: src1:f src2:f len:12
 lcompare:
 local:
 arg:
+oparglist: src1:i len:12
 outarg: src1:i len:1
 outarg_imm: len:5
 retarg:
 setret: dest:a src1:i len:4
-setlret: dest:l src1:i src2:i len:8
+setlret: src1:i src2:i len:12
 setreg: dest:i src1:i len:4 clob:r
 setregimm: dest:i len:8 clob:r
 setfreg: dest:f src1:f len:4 clob:r
 checkthis: src1:b len:4
-voidcall: len:8 clob:c
+voidcall: len:16 clob:c
 voidcall_reg: src1:i len:8 clob:c
-voidcall_membase: src1:b len:8 clob:c
-fcall: dest:f len:8 clob:c
+voidcall_membase: src1:b len:12 clob:c
+fcall: dest:f len:16 clob:c
 fcall_reg: dest:f src1:i len:8 clob:c
-fcall_membase: dest:f src1:b len:8 clob:c
-lcall: dest:l len:8 clob:c
+fcall_membase: dest:f src1:b len:12 clob:c
+lcall: dest:l len:16 clob:c
 lcall_reg: dest:l src1:i len:8 clob:c
-lcall_membase: dest:l src1:b len:8 clob:c
-vcall: len:8 clob:c
+lcall_membase: dest:l src1:b len:12 clob:c
+vcall: len:16 clob:c
 vcall_reg: src1:i len:8 clob:c
-vcall_membase: src1:b len:8 clob:c
-call_reg: dest:i src1:i len:8 clob:c
-call_membase: dest:i src1:b len:8 clob:c
+vcall_membase: src1:b len:12 clob:c
+call_reg: dest:a src1:i len:8 clob:c
+call_membase: dest:a src1:b len:12 clob:c
 trap:
-iconst: dest:i len:8
+iconst: dest:i len:12
 i8const:
-r4const: dest:f len:8
-r8const: dest:f len:8
+r4const: dest:f len:12
+r8const: dest:f len:12
 regvar:
 reg:
 regoffset:
 label:
-store_membase_imm: dest:b len:12
-store_membase_reg: dest:b src1:i len:8
-storei1_membase_imm: dest:b len:12
-storei1_membase_reg: dest:b src1:i len:8
-storei2_membase_imm: dest:b len:12
-storei2_membase_reg: dest:b src1:i len:8
-storei4_membase_imm: dest:b len:12
-storei4_membase_reg: dest:b src1:i len:8
+store_membase_imm: dest:b len:20
+store_membase_reg: dest:b src1:i len:12
+storei1_membase_imm: dest:b len:20
+storei1_membase_reg: dest:b src1:i len:12
+storei2_membase_imm: dest:b len:20
+storei2_membase_reg: dest:b src1:i len:12
+storei4_membase_imm: dest:b len:20
+storei4_membase_reg: dest:b src1:i len:12
 storei8_membase_imm: dest:b 
 storei8_membase_reg: dest:b src1:i 
-storer4_membase_reg: dest:b src1:f len:8
-storer8_membase_reg: dest:b src1:f len:8
+storer4_membase_reg: dest:b src1:f len:16
+storer8_membase_reg: dest:b src1:f len:12
 load_membase: dest:i src1:b len:12
 loadi1_membase: dest:i src1:b len:12
 loadu1_membase: dest:i src1:b len:12
@@ -410,23 +345,24 @@ loadu2_membase: dest:i src1:b len:12
 loadi4_membase: dest:i src1:b len:12
 loadu4_membase: dest:i src1:b len:12
 loadi8_membase: dest:i src1:b
-loadr4_membase: dest:f src1:b len:8
+loadr4_membase: dest:f src1:b len:12
 loadr8_membase: dest:f src1:b len:12
 loadu4_mem: dest:i len:8
 move: dest:i src1:i len:4
+fmove: dest:f src1:f len:4
 add_imm: dest:i src1:i len:12
 sub_imm: dest:i src1:i len:12
 mul_imm: dest:i src1:i len:12
 # there is no actual support for division or reminder by immediate
 # we simulate them, though (but we need to change the burg rules 
 # to allocate a symbolic reg for src2)
-div_imm: dest:a src1:i src2:i len:12
-div_un_imm: dest:a src1:i src2:i len:12
-rem_imm: dest:d src1:i src2:i len:16
-rem_un_imm: dest:d src1:i src2:i len:16
-and_imm: dest:i src1:i len:8
-or_imm: dest:i src1:i len:8
-xor_imm: dest:i src1:i len:8
+div_imm: dest:i src1:i src2:i len:20
+div_un_imm: dest:i src1:i src2:i len:12
+rem_imm: dest:i src1:i src2:i len:28
+rem_un_imm: dest:i src1:i src2:i len:16
+and_imm: dest:i src1:i len:12
+or_imm: dest:i src1:i len:12
+xor_imm: dest:i src1:i len:12
 shl_imm: dest:i src1:i len:8
 shr_imm: dest:i src1:i len:8
 shr_un_imm: dest:i src1:i len:8
@@ -440,9 +376,9 @@ cond_exc_ge: len:8
 cond_exc_ge_un: len:8
 cond_exc_le: len:8
 cond_exc_le_un: len:8
-cond_exc_ov: len:8
+cond_exc_ov: len:12
 cond_exc_no: len:8
-cond_exc_c: len:8
+cond_exc_c: len:12
 cond_exc_nc: len:8
 long_add:
 long_sub:
@@ -470,7 +406,7 @@ long_conv_to_u8:
 long_conv_to_u2:
 long_conv_to_u1:
 long_conv_to_i:
-long_conv_to_ovf_i: dest:i src1:i src2:i len:30
+long_conv_to_ovf_i: dest:i src1:i src2:i len:32
 long_conv_to_ovf_u:
 long_add_ovf:
 long_add_ovf_un:
@@ -528,20 +464,20 @@ float_bge: len:8
 float_bge_un: len:8
 float_ble: len:8
 float_ble_un: len:8
-float_add: len:4
-float_sub: len:4
-float_mul: len:4
-float_div: len:4
-float_div_un: len:4
-float_rem: len:16
-float_rem_un: len:16
+float_add: dest:f src1:f src2:f len:4
+float_sub: dest:f src1:f src2:f len:4
+float_mul: dest:f src1:f src2:f len:4
+float_div: dest:f src1:f src2:f len:4
+float_div_un: dest:f src1:f src2:f len:4
+float_rem: dest:f src1:f src2:f len:16
+float_rem_un: dest:f src1:f src2:f len:16
 float_neg: dest:f src1:f len:4
 float_not: dest:f src1:f len:4
 float_conv_to_i1: dest:i src1:f len:40
 float_conv_to_i2: dest:i src1:f len:40
 float_conv_to_i4: dest:i src1:f len:40
 float_conv_to_i8: dest:l src1:f len:40
-float_conv_to_r4:
+float_conv_to_r4: dest:f src1:f len:4
 float_conv_to_r8:
 float_conv_to_u4: dest:i src1:f len:40
 float_conv_to_u8: dest:l src1:f len:40
@@ -574,14 +510,14 @@ float_conv_to_ovf_i4:
 float_conv_to_ovf_u4:
 float_conv_to_ovf_i8:
 float_conv_to_ovf_u8:
-float_ceq: dest:i src1:f src2:f len:12
-float_cgt: dest:i src1:f src2:f len:12
-float_cgt_un: dest:i src1:f src2:f len:12
-float_clt: dest:i src1:f src2:f len:12
-float_clt_un: dest:i src1:f src2:f len:12
+float_ceq: dest:i src1:f src2:f len:16
+float_cgt: dest:i src1:f src2:f len:16
+float_cgt_un: dest:i src1:f src2:f len:20
+float_clt: dest:i src1:f src2:f len:16
+float_clt_un: dest:i src1:f src2:f len:20
 float_conv_to_u: dest:i src1:f len:36
 call_handler: len:12
-op_endfilter: src1:i len:12
+op_endfilter: src1:i len:16
 aot_const: dest:i len:8
 x86_test_null: src1:i len:4
 x86_compare_membase_reg: src1:b src2:i len:8
@@ -602,12 +538,18 @@ x86_xchg: src1:i src2:i clob:x len:1
 x86_fpop: src1:f len:2
 x86_fp_load_i8: dest:f src1:b len:7
 x86_fp_load_i4: dest:f src1:b len:7
+sqrt: dest:f src1:f len:4
 adc: dest:i src1:i src2:i len:4
 addcc: dest:i src1:i src2:i len:4
 subcc: dest:i src1:i src2:i len:4
-adc_imm: dest:i src1:i len:8
+adc_imm: dest:i src1:i len:12
+addcc_imm: dest:i src1:i len:12
+subcc_imm: dest:i src1:i len:12
 sbb: dest:i src1:i src2:i len:4
-sbb_imm: dest:i src1:i len:8
+sbb_imm: dest:i src1:i len:12
 br_reg: src1:i len:8
 ppc_subfic: dest:i src1:i len:4
 ppc_subfze: dest:i src1:i len:4
+op_bigmul: len:8 dest:l src1:i src2:i
+op_bigmul_un: len:8 dest:l src1:i src2:i
+tls_get: len:8 dest:i