# Copyright 2003-2011 Novell, Inc (http://www.novell.com)
# Copyright 2011 Xamarin, Inc (http://www.xamarin.com)
+# Licensed under the MIT license. See LICENSE file in the project root for full license information.
# arm cpu description file
# this file is read by genmdesc to pruduce a table with all the relevant information
# about the cpu instructions that may be used by the regsiter allocator, the scheduler
#
# register may have the following values:
# i integer register
-# a r3 register (output from calls)
+# a r0 register (first argument/result reg)
# b base register (used in address references)
# f floating point register
# g floating point register returned in r0:r1 for soft-float mode
#
# See the code in mini-x86.c for more details on how the specifiers are used.
#
-memory_barrier: len:8 clob:a
nop: len:4
relaxed_nop: len:4
break: len:4
-jmp: len:92
br: len:16
switch: src1:i len:12
# See the comment in resume_from_signal_handler, we can't copy the fp regs from sigctx to MonoContext on linux,
# since the corresponding sigctx structures are not well defined.
-seq_point: len:38 clob:c
+seq_point: len:52 clob:c
il_seq_point: len:0
throw: src1:i len:24
endfinally: len:32
call_handler: len:16 clob:c
endfilter: src1:i len:16
+get_ex_obj: dest:i len:16
ckfinite: dest:f src1:f len:112
ceq: dest:i len:12
compare: src1:i src2:i len:4
compare_imm: src1:i len:12
fcompare: src1:f src2:f len:12
+rcompare: src1:f src2:f len:12
oparglist: src1:i len:12
setlret: src1:i src2:i len:12
checkthis: src1:b len:4
call: dest:a clob:c len:20
call_reg: dest:a src1:i len:8 clob:c
-call_membase: dest:a src1:b len:24 clob:c
+call_membase: dest:a src1:b len:30 clob:c
voidcall: len:20 clob:c
voidcall_reg: src1:i len:8 clob:c
-voidcall_membase: src1:b len:16 clob:c
+voidcall_membase: src1:b len:24 clob:c
fcall: dest:g len:28 clob:c
fcall_reg: dest:g src1:i len:16 clob:c
-fcall_membase: dest:g src1:b len:24 clob:c
+fcall_membase: dest:g src1:b len:30 clob:c
+rcall: dest:g len:28 clob:c
+rcall_reg: dest:g src1:i len:16 clob:c
+rcall_membase: dest:g src1:b len:30 clob:c
lcall: dest:l len:20 clob:c
lcall_reg: dest:l src1:i len:8 clob:c
-lcall_membase: dest:l src1:b len:16 clob:c
-vcall: len:20 clob:c
-vcall_reg: src1:i len:8 clob:c
-vcall_membase: src1:b len:16 clob:c
+lcall_membase: dest:l src1:b len:24 clob:c
+vcall: len:64 clob:c
+vcall_reg: src1:i len:64 clob:c
+vcall_membase: src1:b len:70 clob:c
tailcall: len:160 clob:c
iconst: dest:i len:16
r4const: dest:f len:24
loadu4_mem: dest:i len:8
move: dest:i src1:i len:4
fmove: dest:f src1:f len:4
+move_f_to_i4: dest:i src1:f len:28
+move_i4_to_f: dest:f src1:i len:8
add_imm: dest:i src1:i len:12
sub_imm: dest:i src1:i len:12
mul_imm: dest:i src1:i len:12
float_cge: dest:y src1:f src2:f len:20
float_cle: dest:y src1:f src2:f len:20
float_conv_to_u: dest:i src1:f len:36
+
+# R4 opcodes
+rmove: dest:f src1:f len:4
+r4_conv_to_i1: dest:i src1:f len:88
+r4_conv_to_i2: dest:i src1:f len:88
+r4_conv_to_i4: dest:i src1:f len:88
+r4_conv_to_u1: dest:i src1:f len:88
+r4_conv_to_u2: dest:i src1:f len:88
+r4_conv_to_u4: dest:i src1:f len:88
+r4_conv_to_r4: dest:f src1:f len:16
+r4_conv_to_r8: dest:f src1:f len:16
+r4_add: dest:f src1:f src2:f len:4
+r4_sub: dest:f src1:f src2:f len:4
+r4_mul: dest:f src1:f src2:f len:4
+r4_div: dest:f src1:f src2:f len:4
+r4_rem: dest:f src1:f src2:f len:16
+r4_neg: dest:f src1:f len:4
+r4_ceq: dest:i src1:f src2:f len:16
+r4_cgt: dest:i src1:f src2:f len:16
+r4_cgt_un: dest:i src1:f src2:f len:20
+r4_clt: dest:i src1:f src2:f len:16
+r4_clt_un: dest:i src1:f src2:f len:20
+r4_cneq: dest:y src1:f src2:f len:20
+r4_cge: dest:y src1:f src2:f len:20
+r4_cle: dest:y src1:f src2:f len:20
+
setfret: src1:f len:12
aot_const: dest:i len:16
objc_get_selector: dest:i len:32
br_reg: src1:i len:8
bigmul: len:8 dest:l src1:i src2:i
bigmul_un: len:8 dest:l src1:i src2:i
-tls_get: len:24 dest:i clob:c
+tls_get: len:16 dest:i
+tls_set: len:16 src1:i clob:c
# 32 bit opcodes
int_add: dest:i src1:i src2:i len:4
long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36
-vcall2: len:20 clob:c
-vcall2_reg: src1:i len:8 clob:c
-vcall2_membase: src1:b len:12 clob:c
-dyn_call: src1:i src2:i len:120 clob:c
+vcall2: len:64 clob:c
+vcall2_reg: src1:i len:64 clob:c
+vcall2_membase: src1:b len:64 clob:c
+dyn_call: src1:i src2:i len:252 clob:c
# This is different from the original JIT opcodes
float_beq: len:32
gc_liveness_use: len:0
gc_spill_slot_liveness_def: len:0
gc_param_slot_liveness_def: len:0
+gc_safe_point: clob:c src1:i len:40
atomic_add_i4: dest:i src1:i src2:i len:64
atomic_exchange_i4: dest:i src1:i src2:i len:64
atomic_cas_i4: dest:i src1:i src2:i src3:i len:64
+memory_barrier: len:8 clob:a
+atomic_load_i1: dest:i src1:b len:28
+atomic_load_u1: dest:i src1:b len:28
+atomic_load_i2: dest:i src1:b len:28
+atomic_load_u2: dest:i src1:b len:28
+atomic_load_i4: dest:i src1:b len:28
+atomic_load_u4: dest:i src1:b len:28
+atomic_load_r4: dest:f src1:b len:80
+atomic_load_r8: dest:f src1:b len:32
+atomic_store_i1: dest:b src1:i len:28
+atomic_store_u1: dest:b src1:i len:28
+atomic_store_i2: dest:b src1:i len:28
+atomic_store_u2: dest:b src1:i len:28
+atomic_store_i4: dest:b src1:i len:28
+atomic_store_u4: dest:b src1:i len:28
+atomic_store_r4: dest:b src1:f len:80
+atomic_store_r8: dest:b src1:f len:32
+
+generic_class_init: src1:a len:44 clob:c
+
+fill_prof_call_ctx: src1:i len:128
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