[llvm] Refactor the calling convention handling code a bit, add support for returning...

[mono.git] / mono / mini / cpu-arm.md

diff --git a/mono/mini/cpu-arm.md b/mono/mini/cpu-arm.md
index 0ff8a13f839d70f0fb2aa495dafc4b64ca3f0de5..9501ea5786becfa463afa63d78cbe8021f37aab8 100644 (file)
--- a/mono/mini/cpu-arm.md
+++ b/mono/mini/cpu-arm.md
@@ -48,7 +48,6 @@
 #
 # See the code in mini-x86.c for more details on how the specifiers are used.
 #
-memory_barrier: len:8 clob:a
 nop: len:4
 relaxed_nop: len:4
 break: len:4
@@ -58,15 +57,16 @@ switch: src1:i len:12
 # See the comment in resume_from_signal_handler, we can't copy the fp regs from sigctx to MonoContext on linux,
 # since the corresponding sigctx structures are not well defined.
 seq_point: len:38 clob:c
+il_seq_point: len:0
 
 throw: src1:i len:24
 rethrow: src1:i len:20
 start_handler: len:20
-endfinally: len:20
+endfinally: len:32
 call_handler: len:16 clob:c
 endfilter: src1:i len:16
 
-ckfinite: dest:f src1:f len:64
+ckfinite: dest:f src1:f len:112
 ceq: dest:i len:12
 cgt: dest:i len:12
 cgt.un: dest:i len:12
@@ -76,6 +76,7 @@ localloc: dest:i src1:i len:60
 compare: src1:i src2:i len:4
 compare_imm: src1:i len:12
 fcompare: src1:f src2:f len:12
+rcompare: src1:f src2:f len:12
 oparglist: src1:i len:12
 setlret: src1:i src2:i len:12
 checkthis: src1:b len:4
@@ -88,12 +89,16 @@ voidcall_membase: src1:b len:16 clob:c
 fcall: dest:g len:28 clob:c
 fcall_reg: dest:g src1:i len:16 clob:c
 fcall_membase: dest:g src1:b len:24 clob:c
+rcall: dest:g len:28 clob:c
+rcall_reg: dest:g src1:i len:16 clob:c
+rcall_membase: dest:g src1:b len:24 clob:c
 lcall: dest:l len:20 clob:c
 lcall_reg: dest:l src1:i len:8 clob:c
 lcall_membase: dest:l src1:b len:16 clob:c
 vcall: len:20 clob:c
 vcall_reg: src1:i len:8 clob:c
 vcall_membase: src1:b len:16 clob:c
+tailcall: len:160 clob:c
 iconst: dest:i len:16
 r4const: dest:f len:24
 r8const: dest:f len:20
@@ -108,7 +113,7 @@ storei4_membase_imm: dest:b len:20
 storei4_membase_reg: dest:b src1:i len:20
 storei8_membase_imm: dest:b 
 storei8_membase_reg: dest:b src1:i 
-storer4_membase_reg: dest:b src1:f len:12
+storer4_membase_reg: dest:b src1:f len:60
 storer8_membase_reg: dest:b src1:f len:24
 store_memindex: dest:b src1:i src2:i len:4
 storei1_memindex: dest:b src1:i src2:i len:4
@@ -122,7 +127,7 @@ loadu2_membase: dest:i src1:b len:4
 loadi4_membase: dest:i src1:b len:4
 loadu4_membase: dest:i src1:b len:4
 loadi8_membase: dest:i src1:b
-loadr4_membase: dest:f src1:b len:8
+loadr4_membase: dest:f src1:b len:56
 loadr8_membase: dest:f src1:b len:24
 load_memindex: dest:i src1:b src2:i len:4
 loadi1_memindex: dest:i src1:b src2:i len:4
@@ -134,6 +139,8 @@ loadu4_memindex: dest:i src1:b src2:i len:4
 loadu4_mem: dest:i len:8
 move: dest:i src1:i len:4
 fmove: dest:f src1:f len:4
+move_f_to_i4: dest:i src1:f len:28
+move_i4_to_f: dest:f src1:i len:8
 add_imm: dest:i src1:i len:12
 sub_imm: dest:i src1:i len:12
 mul_imm: dest:i src1:i len:12
@@ -176,24 +183,53 @@ float_rem: dest:f src1:f src2:f len:16
 float_rem_un: dest:f src1:f src2:f len:16
 float_neg: dest:f src1:f len:4
 float_not: dest:f src1:f len:4
-float_conv_to_i1: dest:i src1:f len:40
-float_conv_to_i2: dest:i src1:f len:40
-float_conv_to_i4: dest:i src1:f len:40
-float_conv_to_i8: dest:l src1:f len:40
+float_conv_to_i1: dest:i src1:f len:88
+float_conv_to_i2: dest:i src1:f len:88
+float_conv_to_i4: dest:i src1:f len:88
+float_conv_to_i8: dest:l src1:f len:88
 float_conv_to_r4: dest:f src1:f len:8
-float_conv_to_u4: dest:i src1:f len:40
-float_conv_to_u8: dest:l src1:f len:40
-float_conv_to_u2: dest:i src1:f len:40
-float_conv_to_u1: dest:i src1:f len:40
+float_conv_to_u4: dest:i src1:f len:88
+float_conv_to_u8: dest:l src1:f len:88
+float_conv_to_u2: dest:i src1:f len:88
+float_conv_to_u1: dest:i src1:f len:88
 float_conv_to_i: dest:i src1:f len:40
 float_ceq: dest:i src1:f src2:f len:16
 float_cgt: dest:i src1:f src2:f len:16
 float_cgt_un: dest:i src1:f src2:f len:20
 float_clt: dest:i src1:f src2:f len:16
 float_clt_un: dest:i src1:f src2:f len:20
+float_cneq: dest:y src1:f src2:f len:20
+float_cge: dest:y src1:f src2:f len:20
+float_cle: dest:y src1:f src2:f len:20
 float_conv_to_u: dest:i src1:f len:36
+
+# R4 opcodes
+r4_conv_to_i1: dest:i src1:f len:88
+r4_conv_to_i2: dest:i src1:f len:88
+r4_conv_to_i4: dest:i src1:f len:88
+r4_conv_to_u1: dest:i src1:f len:88
+r4_conv_to_u2: dest:i src1:f len:88
+r4_conv_to_u4: dest:i src1:f len:88
+r4_conv_to_r4: dest:f src1:f len:16
+r4_conv_to_r8: dest:f src1:f len:16
+r4_add: dest:f src1:f src2:f len:4
+r4_sub: dest:f src1:f src2:f len:4
+r4_mul: dest:f src1:f src2:f len:4
+r4_div: dest:f src1:f src2:f len:4
+r4_rem: dest:f src1:f src2:f len:16
+r4_neg: dest:f src1:f len:4
+r4_ceq: dest:i src1:f src2:f len:16
+r4_cgt: dest:i src1:f src2:f len:16
+r4_cgt_un: dest:i src1:f src2:f len:20
+r4_clt: dest:i src1:f src2:f len:16
+r4_clt_un: dest:i src1:f src2:f len:20
+r4_cneq: dest:y src1:f src2:f len:20
+r4_cge: dest:y src1:f src2:f len:20
+r4_cle: dest:y src1:f src2:f len:20
+
 setfret: src1:f len:12
 aot_const: dest:i len:16
+objc_get_selector: dest:i len:32
 sqrt: dest:f src1:f len:4
 adc: dest:i src1:i src2:i len:4
 addcc: dest:i src1:i src2:i len:4
@@ -206,7 +242,7 @@ sbb_imm: dest:i src1:i len:12
 br_reg: src1:i len:8
 bigmul: len:8 dest:l src1:i src2:i
 bigmul_un: len:8 dest:l src1:i src2:i
-tls_get: len:8 dest:i clob:c
+tls_get: len:24 dest:i clob:c
 
 # 32 bit opcodes
 int_add: dest:i src1:i src2:i len:4
@@ -227,8 +263,8 @@ int_not: dest:i src1:i len:4
 int_conv_to_i1: dest:i src1:i len:8
 int_conv_to_i2: dest:i src1:i len:8
 int_conv_to_i4: dest:i src1:i len:4
-int_conv_to_r4: dest:f src1:i len:36
-int_conv_to_r8: dest:f src1:i len:36
+int_conv_to_r4: dest:f src1:i len:84
+int_conv_to_r8: dest:f src1:i len:84
 int_conv_to_u4: dest:i src1:i
 int_conv_to_r_un: dest:f src1:i len:56
 int_conv_to_u2: dest:i src1:i len:8
@@ -260,6 +296,8 @@ arm_rsc_imm: dest:i src1:i len:4
 # Linear IR opcodes
 dummy_use: src1:i len:0
 dummy_store: len:0
+dummy_iconst: dest:i len:0
+dummy_r8const: dest:f len:0
 not_reached: len:0
 not_null: src1:i len:0
 
@@ -290,6 +328,12 @@ int_cgt_un: dest:i len:12
 int_clt: dest:i len:12
 int_clt_un: dest:i len:12
 
+int_cneq: dest:i len:12
+int_cge: dest:i len:12
+int_cle: dest:i len:12
+int_cge_un: dest:i len:12
+int_cle_un: dest:i len:12
+
 cond_exc_ieq: len:16
 cond_exc_ine_un: len:16
 cond_exc_ilt: len:16
@@ -333,3 +377,24 @@ gc_liveness_def: len:0
 gc_liveness_use: len:0
 gc_spill_slot_liveness_def: len:0
 gc_param_slot_liveness_def: len:0
+
+atomic_add_i4: dest:i src1:i src2:i len:64
+atomic_exchange_i4: dest:i src1:i src2:i len:64
+atomic_cas_i4: dest:i src1:i src2:i src3:i len:64
+memory_barrier: len:8 clob:a
+atomic_load_i1: dest:i src1:b len:28
+atomic_load_u1: dest:i src1:b len:28
+atomic_load_i2: dest:i src1:b len:28
+atomic_load_u2: dest:i src1:b len:28
+atomic_load_i4: dest:i src1:b len:28
+atomic_load_u4: dest:i src1:b len:28
+atomic_load_r4: dest:f src1:b len:80
+atomic_load_r8: dest:f src1:b len:32
+atomic_store_i1: dest:b src1:i len:28
+atomic_store_u1: dest:b src1:i len:28
+atomic_store_i2: dest:b src1:i len:28
+atomic_store_u2: dest:b src1:i len:28
+atomic_store_i4: dest:b src1:i len:28
+atomic_store_u4: dest:b src1:i len:28
+atomic_store_r4: dest:b src1:f len:80
+atomic_store_r8: dest:b src1:f len:32