2008-12-12 Zoltan Varga <vargaz@gmail.com>

[mono.git] / mono / mini / cpu-arm.md

diff --git a/mono/mini/cpu-arm.md b/mono/mini/cpu-arm.md
index 858a0b990565c315fe8a2550059e263a65e96665..07c745fe20a6f5ece16b4cff6b48e183f4c5be67 100644 (file)
--- a/mono/mini/cpu-arm.md
+++ b/mono/mini/cpu-arm.md
@@ -48,6 +48,7 @@
 #
 memory_barrier: len:4
 nop: len:4
+relaxed_nop: len:4
 break: len:4
 jmp: len:92
 br: len:4
@@ -60,7 +61,7 @@ endfinally: len:20
 call_handler: len:12
 endfilter: src1:i len:16
 
-ckfinite: dest:f src1:f len:24
+ckfinite: dest:f src1:f len:64
 ceq: dest:i len:12
 cgt: dest:i len:12
 cgt.un: dest:i len:12
@@ -71,9 +72,6 @@ compare: src1:i src2:i len:4
 compare_imm: src1:i len:12
 fcompare: src1:f src2:f len:12
 oparglist: src1:i len:12
-outarg: src1:i len:1
-outarg_imm: len:16
-setret: dest:a src1:i len:4
 setlret: src1:i src2:i len:12
 checkthis: src1:b len:4
 call: dest:a clob:c len:20
@@ -120,7 +118,7 @@ loadi4_membase: dest:i src1:b len:4
 loadu4_membase: dest:i src1:b len:4
 loadi8_membase: dest:i src1:b
 loadr4_membase: dest:f src1:b len:4
-loadr8_membase: dest:f src1:b len:4
+loadr8_membase: dest:f src1:b len:20
 load_memindex: dest:i src1:b src2:i len:4
 loadi1_memindex: dest:i src1:b src2:i len:4
 loadu1_memindex: dest:i src1:b src2:i len:4
@@ -158,16 +156,16 @@ cond_exc_ov: len:12
 cond_exc_no: len:8
 cond_exc_c: len:12
 cond_exc_nc: len:8
-float_beq: src1:f src2:f len:20
-float_bne_un: src1:f src2:f len:20
-float_blt: src1:f src2:f len:20
-float_blt_un: src1:f src2:f len:20
-float_bgt: src1:f src2:f len:20
-float_bgt_un: src1:f src2:f len:20
-float_bge: src1:f src2:f len:20
-float_bge_un: src1:f src2:f len:20
-float_ble: src1:f src2:f len:20
-float_ble_un: src1:f src2:f len:20
+#float_beq: src1:f src2:f len:20
+#float_bne_un: src1:f src2:f len:20
+#float_blt: src1:f src2:f len:20
+#float_blt_un: src1:f src2:f len:20
+#float_bgt: src1:f src2:f len:20
+#float_bgt_un: src1:f src2:f len:20
+#float_bge: src1:f src2:f len:20
+#float_bge_un: src1:f src2:f len:20
+#float_ble: src1:f src2:f len:20
+#float_ble_un: src1:f src2:f len:20
 float_add: dest:f src1:f src2:f len:4
 float_sub: dest:f src1:f src2:f len:4
 float_mul: dest:f src1:f src2:f len:4
@@ -258,3 +256,72 @@ long_conv_to_ovf_i: dest:i src1:i src2:i len:30
 
 arm_rsbs_imm: dest:i src1:i len:4
 arm_rsc_imm: dest:i src1:i len:4
+
+# Linear IR opcodes
+dummy_use: len:0
+dummy_store: len:0
+not_reached: len:0
+not_null: src1:i len:0
+
+int_adc: dest:i src1:i src2:i len:4
+int_addcc: dest:i src1:i src2:i len:4
+int_subcc: dest:i src1:i src2:i len:4
+int_sbb: dest:i src1:i src2:i len:4
+int_adc_imm: dest:i src1:i len:12
+int_sbb_imm: dest:i src1:i len:12
+
+int_add_imm: dest:i src1:i len:12
+int_sub_imm: dest:i src1:i len:12
+int_mul_imm: dest:i src1:i len:12
+int_div_imm: dest:i src1:i len:20
+int_div_un_imm: dest:i src1:i len:12
+int_rem_imm: dest:i src1:i len:28
+int_rem_un_imm: dest:i src1:i len:16
+int_and_imm: dest:i src1:i len:12
+int_or_imm: dest:i src1:i len:12
+int_xor_imm: dest:i src1:i len:12
+int_shl_imm: dest:i src1:i len:8
+int_shr_imm: dest:i src1:i len:8
+int_shr_un_imm: dest:i src1:i len:8
+
+int_ceq: dest:i len:12
+int_cgt: dest:i len:12
+int_cgt_un: dest:i len:12
+int_clt: dest:i len:12
+int_clt_un: dest:i len:12
+
+cond_exc_ieq: len:8
+cond_exc_ine_un: len:8
+cond_exc_ilt: len:8
+cond_exc_ilt_un: len:8
+cond_exc_igt: len:8
+cond_exc_igt_un: len:8
+cond_exc_ige: len:8
+cond_exc_ige_un: len:8
+cond_exc_ile: len:8
+cond_exc_ile_un: len:8
+cond_exc_iov: len:12
+cond_exc_ino: len:8
+cond_exc_ic: len:12
+cond_exc_inc: len:8
+
+icompare: src1:i src2:i len:4
+icompare_imm: src1:i len:12
+
+long_conv_to_ovf_i4_2: dest:i src1:i src2:i len:36
+
+vcall2: len:20 clob:c
+vcall2_reg: src1:i len:8 clob:c
+vcall2_membase: src1:b len:12 clob:c
+
+# This is different from the original JIT opcodes
+float_beq: len:20
+float_bne_un: len:20
+float_blt: len:20
+float_blt_un: len:20
+float_bgt: len:20
+float_bgt_un: len:20
+float_bge: len:20
+float_bge_un: len:20
+float_ble: len:20
+float_ble_un: len:20