# src1:register describes the first source register of an instruction
# src2:register describes the second source register of an instruction
#
-# register may have the following values:
# i integer register
# b base register (used in address references)
# f floating point register
# a EAX register
-# d EDX register
+# d EDX register
# l long reg (forced eax:edx)
+# s ECX register
+# c register which can be used as a byte register (RAX..RDX)
#
# len:number describe the maximun length in bytes of the instruction
# number is a positive integer. If the length is not specified
#
# clob:spec describe if the instruction clobbers registers or has special needs
#
-# spec can be one of the following characters:
# c clobbers caller-save registers
# 1 clobbers the first source register
# a EAX is clobbered
-# d EAX and EDX are clobbered
-# s the src2 operand needs to be in ECX (shift opcodes)
+# d EDX is clobbered
# x both the source operands are clobbered (xchg)
# m sets an XMM reg
#
# flags:spec describe if the instruction uses or sets the flags (unused)
#
-# spec can be one of the following chars:
# s sets the flags
# u uses the flags
# m uses and modifies the flags
#
# See the code in mini-x86.c for more details on how the specifiers are used.
#
-nop:
+#
+# Native Client Note: NaCl call sequences do not really reach > 32 bytes but
+# the maximum length can be high, so if we get unlucky and wind up trying to
+# emit a call sequence such that we are one or two bytes too long, we need to
+# pad out almost an entire 32 bytes.
+#
+
break: len:2
-jmp: len:42
-br.s:
-brfalse.s:
-brtrue.s:
+jmp: len:120
+tailcall: len:120 clob:c
br: len:6
-brfalse:
-brtrue:
-beq: len:8
-bge: len:8
-bgt: len:8
-ble: len:8
-blt: len:8
-bne.un: len:8
-bge.un: len:8
-bgt.un: len:8
-ble.un: len:8
-blt.un: len:8
-switch:
-ldind.i1: dest:i len:8
-ldind.u1: dest:i len:8
-ldind.i2: dest:i len:8
-ldind.u2: dest:i len:8
-ldind.i4: dest:i len:9
-ldind.u4: dest:i len:8
-ldind.i8:
-ldind.i: dest:i len:8
-ldind.r4:
-ldind.r8:
-ldind.ref: dest:i len:8
-stind.ref: src1:b src2:i
-stind.i1: src1:b src2:i
-stind.i2: src1:b src2:i
-stind.i4: src1:b src2:i
-stind.i8:
-stind.r4: dest:f src1:b
-stind.r8: dest:f src1:b
-add: dest:i src1:i src2:i len:3 clob:1
-sub: dest:i src1:i src2:i len:3 clob:1
-mul: dest:i src1:i src2:i len:4 clob:1
-div: dest:a src1:a src2:i len:16 clob:d
-div.un: dest:a src1:a src2:i len:16 clob:d
-rem: dest:d src1:a src2:i len:16 clob:d
-rem.un: dest:d src1:a src2:i len:16 clob:d
-and: dest:i src1:i src2:i len:3 clob:1
-or: dest:i src1:i src2:i len:3 clob:1
-xor: dest:i src1:i src2:i len:3 clob:1
-shl: dest:i src1:i src2:i clob:s len:3
-shr: dest:i src1:i src2:i clob:s len:3
-shr.un: dest:i src1:i src2:i clob:s len:3
-neg: dest:i src1:i len:3 clob:1
-not: dest:i src1:i len:3 clob:1
-conv.i1: dest:i src1:i len:4
-conv.i2: dest:i src1:i len:4
-conv.i4: dest:i src1:i len:3
-conv.i8: dest:i src1:i len:3
-conv.r4: dest:f src1:i len:9
-conv.r8: dest:f src1:i len:9
-conv.u4: dest:i src1:i len:3
-conv.u8: dest:i src1:i len:3
-callvirt:
-cpobj:
-ldobj:
-ldstr:
-castclass:
-isinst:
-conv.r.un: dest:f src1:i len:8
-unbox:
-throw: src1:i len:18
-op_rethrow: src1:i len:18
-ldfld:
-ldflda:
-stfld:
-ldsfld:
-ldsflda:
-stsfld:
-stobj:
-conv.ovf.i1.un:
-conv.ovf.i2.un:
-conv.ovf.i4.un: dest:i src1:i len:16
-conv.ovf.i8.un:
-conv.ovf.u1.un:
-conv.ovf.u2.un:
-conv.ovf.u4.un:
-conv.ovf.u8.un:
-conv.ovf.i.un:
-conv.ovf.u.un:
-box:
-newarr:
-ldlen:
-ldelema:
-ldelem.i1:
-ldelem.u1:
-ldelem.i2:
-ldelem.u2:
-ldelem.i4:
-ldelem.u4:
-ldelem.i8:
-ldelem.i:
-ldelem.r4:
-ldelem.r8:
-ldelem.ref:
-stelem.i:
-stelem.i1:
-stelem.i2:
-stelem.i4:
-stelem.i8:
-stelem.r4:
-stelem.r8:
-stelem.ref:
-conv.ovf.i1:
-conv.ovf.u1:
-conv.ovf.i2:
-conv.ovf.u2:
-conv.ovf.i4:
-conv.ovf.u4: dest:i src1:i len:15
-conv.ovf.i8:
-conv.ovf.u8:
-refanyval:
+label: len:0
+seq_point: len:25
+
+long_add: dest:i src1:i src2:i len:3 clob:1 nacl:6
+long_sub: dest:i src1:i src2:i len:3 clob:1 nacl:6
+long_mul: dest:i src1:i src2:i len:4 clob:1
+long_div: dest:a src1:a src2:i len:16 clob:d
+long_div_un: dest:a src1:a src2:i len:16 clob:d
+long_rem: dest:d src1:a src2:i len:16 clob:a
+long_rem_un: dest:d src1:a src2:i len:16 clob:a
+long_and: dest:i src1:i src2:i len:3 clob:1
+long_or: dest:i src1:i src2:i len:3 clob:1
+long_xor: dest:i src1:i src2:i len:3 clob:1
+long_shl: dest:i src1:i src2:s clob:1 len:3
+long_shr: dest:i src1:i src2:s clob:1 len:3
+long_shr_un: dest:i src1:i src2:s clob:1 len:3
+long_neg: dest:i src1:i len:3 clob:1
+long_not: dest:i src1:i len:3 clob:1
+long_conv_to_i1: dest:i src1:i len:4
+long_conv_to_i2: dest:i src1:i len:4
+long_conv_to_i4: dest:i src1:i len:3
+long_conv_to_i8: dest:i src1:i len:3
+long_conv_to_r4: dest:f src1:i len:9
+long_conv_to_r8: dest:f src1:i len:9
+long_conv_to_u4: dest:i src1:i len:3
+long_conv_to_u8: dest:i src1:i len:3
+long_conv_to_r_un: dest:f src1:i len:64
+long_conv_to_ovf_i4_un: dest:i src1:i len:16
+long_conv_to_ovf_u4: dest:i src1:i len:15
+long_conv_to_u2: dest:i src1:i len:4
+long_conv_to_u1: dest:i src1:i len:4
+zext_i4: dest:i src1:i len:4
+
+long_mul_imm: dest:i src1:i clob:1 len:12
+long_min: dest:i src1:i src2:i len:16 clob:1
+long_min_un: dest:i src1:i src2:i len:16 clob:1
+long_max: dest:i src1:i src2:i len:16 clob:1
+long_max_un: dest:i src1:i src2:i len:16 clob:1
+
+throw: src1:i len:18 nacl:50
+rethrow: src1:i len:18 nacl:50
+start_handler: len:16
+endfinally: len:9 nacl:22
+endfilter: src1:a len:9 nacl:19
ckfinite: dest:f src1:f len:43
-mkrefany:
-ldtoken:
-conv.u2: dest:i src1:i len:4
-conv.u1: dest:i src1:i len:4
-conv.i: dest:i src1:i len:4
-conv.ovf.i:
-conv.ovf.u:
-add.ovf:
-add.ovf.un:
-mul.ovf: dest:i src1:i src2:i clob:1 len:10
-# this opcode is handled specially in the code generator
-mul.ovf.un: dest:i src1:i src2:i len:18
-sub.ovf:
-sub.ovf.un:
-endfinally:
-leave:
-leave.s:
-stind.i:
-conv.u: dest:i src1:i len:4
-prefix7:
-prefix6:
-prefix5:
-prefix4:
-prefix3:
-prefix2:
-prefix1:
-prefixref:
-arglist:
-ceq: dest:i len:8
-cgt: dest:i len:8
-cgt.un: dest:i len:8
-clt: dest:i len:8
-clt.un: dest:i len:8
-ldftn:
-ldvirtftn:
-ldarg:
-ldarga:
-starg:
-ldloc:
-ldloca:
-stloc:
+ceq: dest:c len:8
+cgt: dest:c len:8
+cgt.un: dest:c len:8
+clt: dest:c len:8
+clt.un: dest:c len:8
localloc: dest:i src1:i len:84
-endfilter:
-unaligned.:
-volatile.:
-tail.:
-initobj:
-cpblk:
-initblk:
-sizeof:
-refanytype:
-illegal:
-endmac:
-mono_objaddr:
-mono_ldptr:
-mono_vtaddr:
-mono_newobj:
-mono_retobj:
-load:
-ldaddr:
-store:
-phi:
-rename:
compare: src1:i src2:i len:3
lcompare: src1:i src2:i len:3
icompare: src1:i src2:i len:3
compare_imm: src1:i len:13
icompare_imm: src1:i len:8
fcompare: src1:f src2:f clob:a len:13
-local:
-arg:
oparglist: src1:b len:11
-outarg: src1:i len:2
-outarg_imm: len:6
-retarg:
-setret: dest:a src1:i len:3
-setlret: dest:i src1:i src2:i len:5
-checkthis: src1:b len:5
-call: dest:a clob:c len:64
-ret: len:2
-voidcall: clob:c len:64
-voidcall_reg: src1:i clob:c len:64
-voidcall_membase: src1:b clob:c len:64
+checkthis: src1:b len:5 nacl:8
+call: dest:a clob:c len:32 nacl:64
+voidcall: clob:c len:32 nacl:64
+voidcall_reg: src1:i clob:c len:32 nacl:64
+voidcall_membase: src1:b clob:c len:32 nacl:64
fcall: dest:f len:64 clob:c
fcall_reg: dest:f src1:i len:64 clob:c
fcall_membase: dest:f src1:b len:64 clob:c
-lcall: dest:i len:64 clob:c
-lcall_reg: dest:i src1:i len:64 clob:c
-lcall_membase: dest:i src1:b len:64 clob:c
+lcall: dest:a len:64 clob:c
+lcall_reg: dest:a src1:i len:64 clob:c
+lcall_membase: dest:a src1:b len:64 clob:c
vcall: len:64 clob:c
vcall_reg: src1:i len:64 clob:c
vcall_membase: src1:b len:64 clob:c
-call_reg: dest:a src1:i len:64 clob:c
-call_membase: dest:a src1:b len:64 clob:c
-trap:
+call_reg: dest:a src1:i len:32 clob:c nacl:64
+call_membase: dest:a src1:b len:32 clob:c nacl:64
iconst: dest:i len:10
-i8const: dest:i len:18
-r4const: dest:f len:13
+i8const: dest:i len:10
+r4const: dest:f len:14
r8const: dest:f len:9
-regvar:
-reg:
-regoffset:
-label:
store_membase_imm: dest:b len:15
-store_membase_reg: dest:b src1:i len:9
-storei8_membase_reg: dest:b src1:i len:9
-storei1_membase_imm: dest:b len:11
-storei1_membase_reg: dest:b src1:i len:9
-storei2_membase_imm: dest:b len:13
-storei2_membase_reg: dest:b src1:i len:9
-storei4_membase_imm: dest:b len:13
-storei4_membase_reg: dest:b src1:i len:9
+store_membase_reg: dest:b src1:i len:9 nacl:11
+storei8_membase_reg: dest:b src1:i len:9 nacl:11
+storei1_membase_imm: dest:b len:11 nacl:15
+storei1_membase_reg: dest:b src1:c len:9 nacl:11
+storei2_membase_imm: dest:b len:13 nacl:15
+storei2_membase_reg: dest:b src1:i len:9 nacl:11
+storei4_membase_imm: dest:b len:13 nacl:15
+storei4_membase_reg: dest:b src1:i len:9 nacl:11
storei8_membase_imm: dest:b len:18
storer4_membase_reg: dest:b src1:f len:15
storer8_membase_reg: dest:b src1:f len:10
-load_membase: dest:i src1:b len:15
-loadi1_membase: dest:i src1:b len:9
-loadu1_membase: dest:i src1:b len:9
-loadi2_membase: dest:i src1:b len:9
-loadu2_membase: dest:i src1:b len:9
-loadi4_membase: dest:i src1:b len:9
-loadu4_membase: dest:i src1:b len:9
-loadi8_membase: dest:i src1:b len:18
+load_membase: dest:i src1:b len:8 nacl:12
+loadi1_membase: dest:c src1:b len:9 nacl:12
+loadu1_membase: dest:c src1:b len:9 nacl:12
+loadi2_membase: dest:i src1:b len:9 nacl:12
+loadu2_membase: dest:i src1:b len:9 nacl:12
+loadi4_membase: dest:i src1:b len:9 nacl:12
+loadu4_membase: dest:i src1:b len:9 nacl:12
+loadi8_membase: dest:i src1:b len:18 nacl:14
loadr4_membase: dest:f src1:b len:16
loadr8_membase: dest:f src1:b len:16
-loadr8_spill_membase: src1:b len:9
loadu4_mem: dest:i len:10
-move: dest:i src1:i len:4
-setreg: dest:i src1:i len:4
-add_imm: dest:i src1:i len:8 clob:1
-sub_imm: dest:i src1:i len:8 clob:1
-mul_imm: dest:i src1:i len:8
-# there is no actual support for division or reminder by immediate
-# we simulate them, though (but we need to change the burg rules
-# to allocate a symbolic reg for src2)
-div_imm: dest:a src1:i src2:i len:16 clob:d
-div_un_imm: dest:a src1:i src2:i len:16 clob:d
-rem_imm: dest:d src1:i src2:i len:16 clob:d
-rem_un_imm: dest:d src1:i src2:i len:16 clob:d
+amd64_loadi8_memindex: dest:i src1:i src2:i len:10
+move: dest:i src1:i len:3
+add_imm: dest:i src1:i len:8 clob:1 nacl:11
+sub_imm: dest:i src1:i len:8 clob:1 nacl:11
+mul_imm: dest:i src1:i len:11
and_imm: dest:i src1:i len:8 clob:1
or_imm: dest:i src1:i len:8 clob:1
xor_imm: dest:i src1:i len:8 clob:1
cond_exc_nc: len:8
cond_exc_iov: len:8
cond_exc_ic: len:8
-long_add:
-long_sub:
-long_mul: dest:i src1:i src2:i clob:1 len:4
-long_mul_imm: dest:i src1:i src2:i clob:1 len:8
-long_div: dest:a src1:a src2:i len:16 clob:d
-long_div_un: dest:a src1:a src2:i len:16 clob:d
-long_rem: dest:d src1:a src2:i len:16 clob:d
-long_rem_un: dest:d src1:a src2:i len:16 clob:d
-long_and:
-long_or:
-long_xor:
-long_shl: dest:i src1:i src2:i clob:s len:31
-long_shr: dest:i src1:i src2:i clob:s len:32
-long_shr_un: dest:i src1:i src2:i clob:s len:32
-long_neg:
-long_not:
-long_conv_to_i1:
-long_conv_to_i2:
-long_conv_to_i4:
-long_conv_to_i8:
-long_conv_to_r4: dest:f src1:i len:8
-long_conv_to_r8: dest:f src1:i len:8
-long_conv_to_u4:
-long_conv_to_u8:
-long_conv_to_u2:
-long_conv_to_u1:
-long_conv_to_i:
-long_conv_to_ovf_i: dest:i src1:i src2:i len:40
-long_conv_to_ovf_u:
-long_add_ovf:
-long_add_ovf_un:
+
long_mul_ovf: dest:i src1:i src2:i clob:1 len:16
long_mul_ovf_un: dest:i src1:i src2:i len:22
-long_sub_ovf:
-long_sub_ovf_un:
-long_conv_to_ovf_i1_un:
-long_conv_to_ovf_i2_un:
-long_conv_to_ovf_i4_un:
-long_conv_to_ovf_i8_un:
-long_conv_to_ovf_u1_un:
-long_conv_to_ovf_u2_un:
-long_conv_to_ovf_u4_un:
-long_conv_to_ovf_u8_un:
-long_conv_to_ovf_i_un:
-long_conv_to_ovf_u_un:
-long_conv_to_ovf_i1:
-long_conv_to_ovf_u1:
-long_conv_to_ovf_i2:
-long_conv_to_ovf_u2:
-long_conv_to_ovf_i4:
-long_conv_to_ovf_u4:
-long_conv_to_ovf_i8:
-long_conv_to_ovf_u8:
-long_ceq:
-long_cgt:
-long_cgt_un:
-long_clt:
-long_clt_un:
-long_conv_to_r_un: dest:f src1:i src2:i len:48
-long_conv_to_u:
long_shr_imm: dest:i src1:i clob:1 len:11
long_shr_un_imm: dest:i src1:i clob:1 len:11
long_shl_imm: dest:i src1:i clob:1 len:11
-long_add_imm:
-long_sub_imm:
-long_beq:
-long_bne_un:
-long_blt:
-long_blt_un:
-long_bgt:
-long_btg_un:
-long_bge:
-long_bge_un:
-long_ble:
-long_ble_un:
+
+long_beq: len:8
+long_bge: len:8
+long_bgt: len:8
+long_ble: len:8
+long_blt: len:8
+long_bne_un: len:8
+long_bge_un: len:8
+long_bgt_un: len:8
+long_ble_un: len:8
+long_blt_un: len:8
+
float_beq: len:13
float_bne_un: len:18
float_blt: len:13
float_blt_un: len:30
float_bgt: len:13
-float_btg_un: len:30
+float_bgt_un: len:30
float_bge: len:32
float_bge_un: len:13
float_ble: len:32
float_ble_un: len:13
-float_add: dest:f src1:f src2:f len:5
-float_sub: dest:f src1:f src2:f len:5
-float_mul: dest:f src1:f src2:f len:5
-float_div: dest:f src1:f src2:f len:5
-float_div_un: dest:f src1:f src2:f len:5
-float_rem: dest:f src1:f src2:f len:19
-float_rem_un: dest:f src1:f src2:f len:19
-float_neg: dest:f src1:f len:19
-float_not: dest:f src1:f len:3
+float_add: dest:f src1:f src2:f clob:1 len:5
+float_sub: dest:f src1:f src2:f clob:1 len:5
+float_mul: dest:f src1:f src2:f clob:1 len:5
+float_div: dest:f src1:f src2:f clob:1 len:5
+float_div_un: dest:f src1:f src2:f clob:1 len:5
+float_rem: dest:f src1:f src2:f clob:1 len:19
+float_rem_un: dest:f src1:f src2:f clob:1 len:19
+float_neg: dest:f src1:f clob:1 len:23
+float_not: dest:f src1:f clob:1 len:3
float_conv_to_i1: dest:i src1:f len:49
float_conv_to_i2: dest:i src1:f len:49
float_conv_to_i4: dest:i src1:f len:49
float_conv_to_i8: dest:i src1:f len:49
-float_conv_to_r4:
-float_conv_to_r8:
float_conv_to_u4: dest:i src1:f len:49
float_conv_to_u8: dest:i src1:f len:49
float_conv_to_u2: dest:i src1:f len:49
float_conv_to_i: dest:i src1:f len:49
float_conv_to_ovf_i: dest:a src1:f len:40
float_conv_to_ovd_u: dest:a src1:f len:40
-float_add_ovf:
-float_add_ovf_un:
float_mul_ovf:
-float_mul_ovf_un:
-float_sub_ovf:
-float_sub_ovf_un:
-float_conv_to_ovf_i1_un:
-float_conv_to_ovf_i2_un:
-float_conv_to_ovf_i4_un:
-float_conv_to_ovf_i8_un:
-float_conv_to_ovf_u1_un:
-float_conv_to_ovf_u2_un:
-float_conv_to_ovf_u4_un:
-float_conv_to_ovf_u8_un:
-float_conv_to_ovf_i_un:
-float_conv_to_ovf_u_un:
-float_conv_to_ovf_i1:
-float_conv_to_ovf_u1:
-float_conv_to_ovf_i2:
-float_conv_to_ovf_u2:
-float_conv_to_ovf_i4:
-float_conv_to_ovf_u4:
-float_conv_to_ovf_i8:
-float_conv_to_ovf_u8:
float_ceq: dest:i src1:f src2:f len:35
float_cgt: dest:i src1:f src2:f len:35
float_cgt_un: dest:i src1:f src2:f len:48
float_clt_un_membase: dest:i src1:f src2:b len:42
float_conv_to_u: dest:i src1:f len:46
fmove: dest:f src1:f len:8
-call_handler: len:14
+call_handler: len:14 clob:c nacl:52
aot_const: dest:i len:10
+nacl_gc_safe_point: clob:c
x86_test_null: src1:i len:5
x86_compare_membase_reg: src1:b src2:i len:9
x86_compare_membase_imm: src1:b len:13
x86_push_membase: src1:b len:8
x86_push_obj: src1:b len:40
x86_lea: dest:i src1:i src2:i len:8
-x86_lea_membase: dest:i src1:i len:11
+x86_lea_membase: dest:i src1:i len:11 nacl:14
x86_xchg: src1:i src2:i clob:x len:2
x86_fpop: src1:f len:3
-x86_fp_load_i8: dest:f src1:b len:8
-x86_fp_load_i4: dest:f src1:b len:8
x86_seteq_membase: src1:b len:9
-x86_add_membase: dest:i src1:i src2:b clob:1 len:13
-x86_sub_membase: dest:i src1:i src2:b clob:1 len:13
-x86_mul_membase: dest:i src1:i src2:b clob:1 len:14
-tls_get: dest:i len:13
+
+x86_add_reg_membase: dest:i src1:i src2:b clob:1 len:13
+x86_sub_reg_membase: dest:i src1:i src2:b clob:1 len:13
+x86_mul_reg_membase: dest:i src1:i src2:b clob:1 len:13
+x86_and_reg_membase: dest:i src1:i src2:b clob:1 len:13
+x86_or_reg_membase: dest:i src1:i src2:b clob:1 len:13
+x86_xor_reg_membase: dest:i src1:i src2:b clob:1 len:13
+
amd64_test_null: src1:i len:5
amd64_icompare_membase_reg: src1:b src2:i len:8
amd64_icompare_membase_imm: src1:b len:13
amd64_icompare_reg_membase: src1:i src2:b len:8
amd64_set_xmmreg_r4: dest:f src1:f len:14 clob:m
amd64_set_xmmreg_r8: dest:f src1:f len:14 clob:m
+amd64_save_sp_to_lmf: len:16
+tls_get: dest:i len:16
atomic_add_i4: src1:b src2:i dest:i len:32
atomic_add_new_i4: src1:b src2:i dest:i len:32
-atomic_exchange_i4: src1:b src2:i dest:i len:32
+atomic_exchange_i4: src1:b src2:i dest:a len:32
atomic_add_i8: src1:b src2:i dest:i len:32
atomic_add_new_i8: src1:b src2:i dest:i len:32
-atomic_exchange_i8: src1:b src2:i dest:i len:32
+atomic_exchange_i8: src1:b src2:i dest:a len:32
+atomic_cas_i4: src1:b src2:i src3:a dest:a len:24
+atomic_cas_i8: src1:b src2:i src3:a dest:a len:24
+memory_barrier: len:16
adc: dest:i src1:i src2:i len:3 clob:1
addcc: dest:i src1:i src2:i len:3 clob:1
subcc: dest:i src1:i src2:i len:3 clob:1
adc_imm: dest:i src1:i len:8 clob:1
sbb: dest:i src1:i src2:i len:3 clob:1
sbb_imm: dest:i src1:i len:8 clob:1
-br_reg: src1:i len:3
+br_reg: src1:i len:3 nacl:8
sin: dest:f src1:f len:32
cos: dest:f src1:f len:32
-abs: dest:f src1:f len:32
+abs: dest:f src1:f clob:1 len:32
tan: dest:f src1:f len:59
atan: dest:f src1:f len:9
sqrt: dest:f src1:f len:32
-op_bigmul: len:3 dest:i src1:a src2:i
-op_bigmul_un: len:3 dest:i src1:a src2:i
sext_i1: dest:i src1:i len:4
sext_i2: dest:i src1:i len:4
+sext_i4: dest:i src1:i len:8
# 32 bit opcodes
-# FIXME: fix sizes
-int_add: dest:i src1:i src2:i clob:1 len:64
-int_sub: dest:i src1:i src2:i clob:1 len:64
-int_mul: dest:i src1:i src2:i clob:1 len:64
-int_mul_ovf: dest:i src1:i src2:i clob:1 len:64
-int_mul_ovf_un: dest:i src1:i src2:i clob:1 len:64
-int_div: dest:a src1:a src2:i clob:d len:64
-int_div_un: dest:a src1:a src2:i clob:d len:64
-int_rem: dest:d src1:a src2:i clob:d len:64
-int_rem_un: dest:d src1:a src2:i clob:d len:64
-int_and: dest:i src1:i src2:i clob:1 len:64
-int_or: dest:i src1:i src2:i clob:1 len:64
-int_xor: dest:i src1:i src2:i clob:1 len:64
-int_shl: dest:i src1:i src2:i clob:s len:64
-int_shr: dest:i src1:i src2:i clob:s len:64
-int_shr_un: dest:i src1:i src2:i clob:s len:64
-int_adc: dest:i src1:i src2:i clob:1 len:64
-int_adc_imm: dest:i src1:i clob:1 len:64
-int_sbb: dest:i src1:i src2:i clob:1 len:64
-int_sbb_imm: dest:i src1:i clob:1 len:64
-int_addcc: dest:i src1:i src2:i clob:1 len:64
-int_subcc: dest:i src1:i src2:i clob:1 len:64
-int_add_imm: dest:i src1:i clob:1 len:64
-int_sub_imm: dest:i src1:i clob:1 len:64
-int_mul_imm: dest:i src1:i clob:1 len:64
-int_div_imm: dest:a src1:i clob:d len:64
-int_div_un_imm: dest:a src1:i clob:d len:64
-int_rem_imm: dest:d src1:i clob:d len:64
-int_rem_un_imm: dest:d src1:i clob:d len:64
-int_and_imm: dest:i src1:i clob:1 len:64
-int_or_imm: dest:i src1:i clob:1 len:64
-int_xor_imm: dest:i src1:i clob:1 len:64
-int_shl_imm: dest:i src1:i clob:1 len:64
-int_shr_imm: dest:i src1:i clob:1 len:64
-int_shr_un_imm: dest:i src1:i clob:1 len:64
-int_neg: dest:i src1:i clob:1 len:64
-int_not: dest:i src1:i clob:1 len:64
-int_ceq: dest:i len:64
-int_cgt: dest:i len:64
-int_cgt_un: dest:i len:64
-int_clt: dest:i len:64
-int_clt_un: dest:i len:64
-int_beq: len:64
-int_bne_un: len:64
-int_blt: len:64
-int_blt_un: len:64
-int_bgt: len:64
-int_bgt_un: len:64
-int_bge: len:64
-int_bge_un: len:64
-int_ble: len:64
-int_ble_un: len:64
+int_add: dest:i src1:i src2:i clob:1 len:4 nacl:7
+int_sub: dest:i src1:i src2:i clob:1 len:4 nacl:7
+int_mul: dest:i src1:i src2:i clob:1 len:4
+int_mul_ovf: dest:i src1:i src2:i clob:1 len:32
+int_mul_ovf_un: dest:i src1:i src2:i clob:1 len:32
+int_div: dest:a src1:a src2:i clob:d len:32
+int_div_un: dest:a src1:a src2:i clob:d len:32
+int_rem: dest:d src1:a src2:i clob:a len:32
+int_rem_un: dest:d src1:a src2:i clob:a len:32
+int_and: dest:i src1:i src2:i clob:1 len:4
+int_or: dest:i src1:i src2:i clob:1 len:4
+int_xor: dest:i src1:i src2:i clob:1 len:4
+int_shl: dest:i src1:i src2:s clob:1 len:4
+int_shr: dest:i src1:i src2:s clob:1 len:4
+int_shr_un: dest:i src1:i src2:s clob:1 len:4
+int_adc: dest:i src1:i src2:i clob:1 len:4
+int_adc_imm: dest:i src1:i clob:1 len:8
+int_sbb: dest:i src1:i src2:i clob:1 len:4
+int_sbb_imm: dest:i src1:i clob:1 len:8
+int_addcc: dest:i src1:i src2:i clob:1 len:16
+int_subcc: dest:i src1:i src2:i clob:1 len:16
+int_add_imm: dest:i src1:i clob:1 len:8 nacl:10
+int_sub_imm: dest:i src1:i clob:1 len:8 nacl:10
+int_mul_imm: dest:i src1:i clob:1 len:32
+int_div_imm: dest:a src1:i clob:d len:32
+int_div_un_imm: dest:a src1:i clob:d len:32
+int_rem_imm: dest:a src1:a len:32 clob:d
+int_rem_un_imm: dest:d src1:i clob:a len:32
+int_and_imm: dest:i src1:i clob:1 len:8
+int_or_imm: dest:i src1:i clob:1 len:8
+int_xor_imm: dest:i src1:i clob:1 len:8
+int_shl_imm: dest:i src1:i clob:1 len:8
+int_shr_imm: dest:i src1:i clob:1 len:8
+int_shr_un_imm: dest:i src1:i clob:1 len:8
+int_min: dest:i src1:i src2:i len:16 clob:1
+int_max: dest:i src1:i src2:i len:16 clob:1
+int_min_un: dest:i src1:i src2:i len:16 clob:1
+int_max_un: dest:i src1:i src2:i len:16 clob:1
+
+int_neg: dest:i src1:i clob:1 len:4
+int_not: dest:i src1:i clob:1 len:4
+int_conv_to_r4: dest:f src1:i len:9
+int_conv_to_r8: dest:f src1:i len:9
+int_ceq: dest:c len:8
+int_cgt: dest:c len:8
+int_cgt_un: dest:c len:8
+int_clt: dest:c len:8
+int_clt_un: dest:c len:8
+int_beq: len:8
+int_bne_un: len:8
+int_blt: len:8
+int_blt_un: len:8
+int_bgt: len:8
+int_bgt_un: len:8
+int_bge: len:8
+int_bge_un: len:8
+int_ble: len:8
+int_ble_un: len:8
+
+card_table_wbarrier: src1:a src2:i clob:d len:42
+
+relaxed_nop: len:2
+hard_nop: len:1
+
+# Linear IR opcodes
+nop: len:0
+dummy_use: src1:i len:0
+dummy_store: len:0
+not_reached: len:0
+not_null: src1:i len:0
+
+long_ceq: dest:c len:64
+long_cgt: dest:c len:64
+long_cgt_un: dest:c len:64
+long_clt: dest:c len:64
+long_clt_un: dest:c len:64
+
+int_conv_to_i1: dest:i src1:i len:4
+int_conv_to_i2: dest:i src1:i len:4
+int_conv_to_i4: dest:i src1:i len:3
+int_conv_to_i8: dest:i src1:i len:3
+int_conv_to_u4: dest:i src1:i len:3
+int_conv_to_u8: dest:i src1:i len:3
+
+int_conv_to_u: dest:i src1:i len:4
+int_conv_to_u2: dest:i src1:i len:4
+int_conv_to_u1: dest:i src1:i len:4
+int_conv_to_i: dest:i src1:i len:4
+
+cond_exc_ieq: len:8
+cond_exc_ine_un: len:8
+cond_exc_ilt: len:8
+cond_exc_ilt_un: len:8
+cond_exc_igt: len:8
+cond_exc_igt_un: len:8
+cond_exc_ige: len:8
+cond_exc_ige_un: len:8
+cond_exc_ile: len:8
+cond_exc_ile_un: len:8
+cond_exc_ino: len:8
+cond_exc_inc: len:8
+
+x86_compare_membase8_imm: src1:b len:9
+
+jump_table: dest:i len:18
+
+cmov_ieq: dest:i src1:i src2:i len:16 clob:1
+cmov_ige: dest:i src1:i src2:i len:16 clob:1
+cmov_igt: dest:i src1:i src2:i len:16 clob:1
+cmov_ile: dest:i src1:i src2:i len:16 clob:1
+cmov_ilt: dest:i src1:i src2:i len:16 clob:1
+cmov_ine_un: dest:i src1:i src2:i len:16 clob:1
+cmov_ige_un: dest:i src1:i src2:i len:16 clob:1
+cmov_igt_un: dest:i src1:i src2:i len:16 clob:1
+cmov_ile_un: dest:i src1:i src2:i len:16 clob:1
+cmov_ilt_un: dest:i src1:i src2:i len:16 clob:1
+
+cmov_leq: dest:i src1:i src2:i len:16 clob:1
+cmov_lge: dest:i src1:i src2:i len:16 clob:1
+cmov_lgt: dest:i src1:i src2:i len:16 clob:1
+cmov_lle: dest:i src1:i src2:i len:16 clob:1
+cmov_llt: dest:i src1:i src2:i len:16 clob:1
+cmov_lne_un: dest:i src1:i src2:i len:16 clob:1
+cmov_lge_un: dest:i src1:i src2:i len:16 clob:1
+cmov_lgt_un: dest:i src1:i src2:i len:16 clob:1
+cmov_lle_un: dest:i src1:i src2:i len:16 clob:1
+cmov_llt_un: dest:i src1:i src2:i len:16 clob:1
+
+long_add_imm: dest:i src1:i clob:1 len:12 nacl:15
+long_sub_imm: dest:i src1:i clob:1 len:12 nacl:15
+long_and_imm: dest:i src1:i clob:1 len:12
+long_or_imm: dest:i src1:i clob:1 len:12
+long_xor_imm: dest:i src1:i clob:1 len:12
+
+lcompare_imm: src1:i len:13
+
+amd64_compare_membase_reg: src1:b src2:i len:9
+amd64_compare_membase_imm: src1:b len:14
+amd64_compare_reg_membase: src1:i src2:b len:9
+
+amd64_add_reg_membase: dest:i src1:i src2:b clob:1 len:14
+amd64_sub_reg_membase: dest:i src1:i src2:b clob:1 len:14
+amd64_and_reg_membase: dest:i src1:i src2:b clob:1 len:14
+amd64_or_reg_membase: dest:i src1:i src2:b clob:1 len:14
+amd64_xor_reg_membase: dest:i src1:i src2:b clob:1 len:14
+
+amd64_add_membase_imm: src1:b len:16
+amd64_sub_membase_imm: src1:b len:16
+amd64_and_membase_imm: src1:b len:13
+amd64_or_membase_imm: src1:b len:13
+amd64_xor_membase_imm: src1:b len:13
+
+x86_and_membase_imm: src1:b len:12
+x86_or_membase_imm: src1:b len:12
+x86_xor_membase_imm: src1:b len:12
+
+x86_add_membase_reg: src1:b src2:i len:12
+x86_sub_membase_reg: src1:b src2:i len:12
+x86_and_membase_reg: src1:b src2:i len:12
+x86_or_membase_reg: src1:b src2:i len:12
+x86_xor_membase_reg: src1:b src2:i len:12
+x86_mul_membase_reg: src1:b src2:i len:14
+
+amd64_add_membase_reg: src1:b src2:i len:13
+amd64_sub_membase_reg: src1:b src2:i len:13
+amd64_and_membase_reg: src1:b src2:i len:13
+amd64_or_membase_reg: src1:b src2:i len:13
+amd64_xor_membase_reg: src1:b src2:i len:13
+amd64_mul_membase_reg: src1:b src2:i len:15
+
+float_conv_to_r4: dest:f src1:f
+
+vcall2: len:64 clob:c
+vcall2_reg: src1:i len:64 clob:c
+vcall2_membase: src1:b len:64 clob:c
+
+dyn_call: src1:i src2:i len:64 clob:c nacl:128
+
+localloc_imm: dest:i len:84
+
+load_mem: dest:i len:16
+loadi8_mem: dest:i len:16
+loadi4_mem: dest:i len:16
+loadu1_mem: dest:i len:16
+loadu2_mem: dest:i len:16
+
+
+#SIMD
+
+addps: dest:x src1:x src2:x len:4 clob:1
+divps: dest:x src1:x src2:x len:4 clob:1
+mulps: dest:x src1:x src2:x len:4 clob:1
+subps: dest:x src1:x src2:x len:4 clob:1
+maxps: dest:x src1:x src2:x len:4 clob:1
+minps: dest:x src1:x src2:x len:4 clob:1
+compps: dest:x src1:x src2:x len:5 clob:1
+andps: dest:x src1:x src2:x len:4 clob:1
+andnps: dest:x src1:x src2:x len:4 clob:1
+orps: dest:x src1:x src2:x len:4 clob:1
+xorps: dest:x src1:x src2:x len:4 clob:1
+
+haddps: dest:x src1:x src2:x len:5 clob:1
+hsubps: dest:x src1:x src2:x len:5 clob:1
+addsubps: dest:x src1:x src2:x len:5 clob:1
+dupps_low: dest:x src1:x len:5
+dupps_high: dest:x src1:x len:5
+
+addpd: dest:x src1:x src2:x len:5 clob:1
+divpd: dest:x src1:x src2:x len:5 clob:1
+mulpd: dest:x src1:x src2:x len:5 clob:1
+subpd: dest:x src1:x src2:x len:5 clob:1
+maxpd: dest:x src1:x src2:x len:5 clob:1
+minpd: dest:x src1:x src2:x len:5 clob:1
+comppd: dest:x src1:x src2:x len:6 clob:1
+andpd: dest:x src1:x src2:x len:5 clob:1
+andnpd: dest:x src1:x src2:x len:5 clob:1
+orpd: dest:x src1:x src2:x len:5 clob:1
+xorpd: dest:x src1:x src2:x len:5 clob:1
+sqrtpd: dest:x src1:x len:5 clob:1
+
+haddpd: dest:x src1:x src2:x len:6 clob:1
+hsubpd: dest:x src1:x src2:x len:6 clob:1
+addsubpd: dest:x src1:x src2:x len:6 clob:1
+duppd: dest:x src1:x len:6
+
+pand: dest:x src1:x src2:x len:5 clob:1
+por: dest:x src1:x src2:x len:5 clob:1
+pxor: dest:x src1:x src2:x len:5 clob:1
+
+sqrtps: dest:x src1:x len:5
+rsqrtps: dest:x src1:x len:5
+rcpps: dest:x src1:x len:5
+
+pshufflew_high: dest:x src1:x len:6
+pshufflew_low: dest:x src1:x len:6
+pshuffled: dest:x src1:x len:6
+
+extract_mask: dest:i src1:x len:6
+
+paddb: dest:x src1:x src2:x len:5 clob:1
+paddw: dest:x src1:x src2:x len:5 clob:1
+paddd: dest:x src1:x src2:x len:5 clob:1
+paddq: dest:x src1:x src2:x len:5 clob:1
+
+psubb: dest:x src1:x src2:x len:5 clob:1
+psubw: dest:x src1:x src2:x len:5 clob:1
+psubd: dest:x src1:x src2:x len:5 clob:1
+psubq: dest:x src1:x src2:x len:5 clob:1
+
+pmaxb_un: dest:x src1:x src2:x len:5 clob:1
+pmaxw_un: dest:x src1:x src2:x len:6 clob:1
+pmaxd_un: dest:x src1:x src2:x len:6 clob:1
+
+pmaxb: dest:x src1:x src2:x len:6 clob:1
+pmaxw: dest:x src1:x src2:x len:5 clob:1
+pmaxd: dest:x src1:x src2:x len:6 clob:1
+
+pavgb_un: dest:x src1:x src2:x len:5 clob:1
+pavgw_un: dest:x src1:x src2:x len:5 clob:1
+
+pminb_un: dest:x src1:x src2:x len:5 clob:1
+pminw_un: dest:x src1:x src2:x len:6 clob:1
+pmind_un: dest:x src1:x src2:x len:6 clob:1
+
+pminb: dest:x src1:x src2:x len:6 clob:1
+pminw: dest:x src1:x src2:x len:5 clob:1
+pmind: dest:x src1:x src2:x len:6 clob:1
+
+pcmpeqb: dest:x src1:x src2:x len:5 clob:1
+pcmpeqw: dest:x src1:x src2:x len:5 clob:1
+pcmpeqd: dest:x src1:x src2:x len:5 clob:1
+pcmpeqq: dest:x src1:x src2:x len:6 clob:1
+
+pcmpgtb: dest:x src1:x src2:x len:5 clob:1
+pcmpgtw: dest:x src1:x src2:x len:5 clob:1
+pcmpgtd: dest:x src1:x src2:x len:5 clob:1
+pcmpgtq: dest:x src1:x src2:x len:6 clob:1
+
+psumabsdiff: dest:x src1:x src2:x len:5 clob:1
+
+unpack_lowb: dest:x src1:x src2:x len:5 clob:1
+unpack_loww: dest:x src1:x src2:x len:5 clob:1
+unpack_lowd: dest:x src1:x src2:x len:5 clob:1
+unpack_lowq: dest:x src1:x src2:x len:5 clob:1
+unpack_lowps: dest:x src1:x src2:x len:5 clob:1
+unpack_lowpd: dest:x src1:x src2:x len:5 clob:1
+
+unpack_highb: dest:x src1:x src2:x len:5 clob:1
+unpack_highw: dest:x src1:x src2:x len:5 clob:1
+unpack_highd: dest:x src1:x src2:x len:5 clob:1
+unpack_highq: dest:x src1:x src2:x len:5 clob:1
+unpack_highps: dest:x src1:x src2:x len:5 clob:1
+unpack_highpd: dest:x src1:x src2:x len:5 clob:1
+
+packw: dest:x src1:x src2:x len:5 clob:1
+packd: dest:x src1:x src2:x len:5 clob:1
+
+packw_un: dest:x src1:x src2:x len:5 clob:1
+packd_un: dest:x src1:x src2:x len:6 clob:1
+
+paddb_sat: dest:x src1:x src2:x len:5 clob:1
+paddb_sat_un: dest:x src1:x src2:x len:5 clob:1
+
+paddw_sat: dest:x src1:x src2:x len:5 clob:1
+paddw_sat_un: dest:x src1:x src2:x len:5 clob:1
+
+psubb_sat: dest:x src1:x src2:x len:5 clob:1
+psubb_sat_un: dest:x src1:x src2:x len:5 clob:1
+
+psubw_sat: dest:x src1:x src2:x len:5 clob:1
+psubw_sat_un: dest:x src1:x src2:x len:5 clob:1
+
+pmulw: dest:x src1:x src2:x len:5 clob:1
+pmuld: dest:x src1:x src2:x len:6 clob:1
+pmulq: dest:x src1:x src2:x len:5 clob:1
+
+pmul_high_un: dest:x src1:x src2:x len:5 clob:1
+pmul_high: dest:x src1:x src2:x len:5 clob:1
+
+pshrw: dest:x src1:x len:6 clob:1
+pshrw_reg: dest:x src1:x src2:x len:5 clob:1
+
+psarw: dest:x src1:x len:6 clob:1
+psarw_reg: dest:x src1:x src2:x len:5 clob:1
+
+pshlw: dest:x src1:x len:6 clob:1
+pshlw_reg: dest:x src1:x src2:x len:5 clob:1
+
+pshrd: dest:x src1:x len:6 clob:1
+pshrd_reg: dest:x src1:x src2:x len:5 clob:1
+
+psard: dest:x src1:x len:6 clob:1
+psard_reg: dest:x src1:x src2:x len:5 clob:1
+
+pshld: dest:x src1:x len:6 clob:1
+pshld_reg: dest:x src1:x src2:x len:5 clob:1
+
+pshrq: dest:x src1:x len:6 clob:1
+pshrq_reg: dest:x src1:x src2:x len:5 clob:1
+
+pshlq: dest:x src1:x len:6 clob:1
+pshlq_reg: dest:x src1:x src2:x len:5 clob:1
+
+xmove: dest:x src1:x len:5
+xzero: dest:x len:5
+
+iconv_to_x: dest:x src1:i len:5
+extract_i4: dest:i src1:x len:5
+
+extract_i8: dest:i src1:x len:9
+
+extract_i2: dest:i src1:x len:13
+extract_u2: dest:i src1:x len:13
+extract_i1: dest:i src1:x len:13
+extract_u1: dest:i src1:x len:13
+extract_r8: dest:f src1:x len:5
+
+iconv_to_r8_raw: dest:f src1:i len:10
+
+insert_i2: dest:x src1:x src2:i len:6 clob:1
+
+extractx_u2: dest:i src1:x len:6
+insertx_u1_slow: dest:x src1:i src2:i len:18 clob:x
+
+insertx_i4_slow: dest:x src1:x src2:i len:16 clob:x
+insertx_i8_slow: dest:x src1:x src2:i len:13
+insertx_r4_slow: dest:x src1:x src2:f len:24
+insertx_r8_slow: dest:x src1:x src2:f len:24
+
+loadx_membase: dest:x src1:b len:9
+storex_membase: dest:b src1:x len:9
+storex_membase_reg: dest:b src1:x len:9
+
+loadx_aligned_membase: dest:x src1:b len:7
+storex_aligned_membase_reg: dest:b src1:x len:7
+storex_nta_membase_reg: dest:b src1:x len:7
+
+fconv_to_r8_x: dest:x src1:f len:4
+xconv_r8_to_i4: dest:y src1:x len:7
+
+prefetch_membase: src1:b len:4
+
+expand_i2: dest:x src1:i len:18
+expand_i4: dest:x src1:i len:11
+expand_i8: dest:x src1:i len:11
+expand_r4: dest:x src1:f len:16
+expand_r8: dest:x src1:f len:13
+
+liverange_start: len:0
+liverange_end: len:0
+gc_liveness_def: len:0
+gc_liveness_use: len:0
+gc_spill_slot_liveness_def: len:0
+gc_param_slot_liveness_def: len:0
projects / mono.git / blobdiff