2005-07-08 Zoltan Varga <vargaz@freemail.hu>

[mono.git] / mono / mini / cpu-amd64.md

diff --git a/mono/mini/cpu-amd64.md b/mono/mini/cpu-amd64.md
index 19c98e7a8767700b0d48caae809fc9250987ab48..7277d3479e2724ed41e4a45f550048579581225d 100644 (file)
--- a/mono/mini/cpu-amd64.md
+++ b/mono/mini/cpu-amd64.md
@@ -16,9 +16,10 @@
 #      b  base register (used in address references)
 #      f  floating point register
 #      a  EAX register
-#       d  EDX register
+#   d  EDX register
 #      l  long reg (forced eax:edx)
-#              L  long reg (dynamic)
+#   s  ECX register
+#   c  register which can be used as a byte register (RAX..RDX)
 #
 # len:number         describe the maximun length in bytes of the instruction
 #                   number is a positive integer.  If the length is not specified
@@ -35,9 +36,9 @@
 #      c  clobbers caller-save registers
 #      1  clobbers the first source register
 #      a  EAX is clobbered
-#   d  EAX and EDX are clobbered
-#      s  the src2 operand needs to be in ECX (shift opcodes)
+#   d  EDX is clobbered
 #      x  both the source operands are clobbered (xchg)
+#   m  sets an XMM reg
 #
 # flags:spec        describe if the instruction uses or sets the flags (unused)
 #
@@ -64,28 +65,28 @@ brtrue.s:
 br: len:6
 brfalse:
 brtrue:
-beq: len:7
-bge: len:7
-bgt: len:7
-ble: len:7
-blt: len:7
-bne.un: len:7
-bge.un: len:7
-bgt.un: len:7
-ble.un: len:7
-blt.un: len:7
+beq: len:8
+bge: len:8
+bgt: len:8
+ble: len:8
+blt: len:8
+bne.un: len:8
+bge.un: len:8
+bgt.un: len:8
+ble.un: len:8
+blt.un: len:8
 switch:
-ldind.i1: dest:i len:7
-ldind.u1: dest:i len:7
-ldind.i2: dest:i len:7
-ldind.u2: dest:i len:7
+ldind.i1: dest:i len:8
+ldind.u1: dest:i len:8
+ldind.i2: dest:i len:8
+ldind.u2: dest:i len:8
 ldind.i4: dest:i len:9
-ldind.u4: dest:i len:7
+ldind.u4: dest:i len:8
 ldind.i8:
-ldind.i: dest:i len:7
+ldind.i: dest:i len:8
 ldind.r4:
 ldind.r8:
-ldind.ref: dest:i len:7
+ldind.ref: dest:i len:8
 stind.ref: src1:b src2:i
 stind.i1: src1:b src2:i
 stind.i2: src1:b src2:i
@@ -96,16 +97,16 @@ stind.r8: dest:f src1:b
 add: dest:i src1:i src2:i len:3 clob:1
 sub: dest:i src1:i src2:i len:3 clob:1
 mul: dest:i src1:i src2:i len:4 clob:1
-div: dest:a src1:i src2:i len:16 clob:d
-div.un: dest:a src1:i src2:i len:16 clob:d
-rem: dest:d src1:i src2:i len:16 clob:d
-rem.un: dest:d src1:i src2:i len:16 clob:d
+div: dest:a src1:a src2:i len:16 clob:d
+div.un: dest:a src1:a src2:i len:16 clob:d
+rem: dest:d src1:a src2:i len:16 clob:a
+rem.un: dest:d src1:a src2:i len:16 clob:a
 and: dest:i src1:i src2:i len:3 clob:1
 or: dest:i src1:i src2:i len:3 clob:1
 xor: dest:i src1:i src2:i len:3 clob:1
-shl: dest:i src1:i src2:i clob:s len:3
-shr: dest:i src1:i src2:i clob:s len:3
-shr.un: dest:i src1:i src2:i clob:s len:3
+shl: dest:i src1:i src2:s clob:1 len:3
+shr: dest:i src1:i src2:s clob:1 len:3
+shr.un: dest:i src1:i src2:s clob:1 len:3
 neg: dest:i src1:i len:3 clob:1
 not: dest:i src1:i len:3 clob:1
 conv.i1: dest:i src1:i len:4
@@ -114,18 +115,18 @@ conv.i4: dest:i src1:i len:3
 conv.i8: dest:i src1:i len:3
 conv.r4: dest:f src1:i len:9
 conv.r8: dest:f src1:i len:9
-conv.u4: dest:i src1:i
+conv.u4: dest:i src1:i len:3
 conv.u8: dest:i src1:i len:3
 callvirt:
 cpobj:
 ldobj:
 ldstr:
-newobj:
 castclass:
 isinst:
-conv.r.un:
+conv.r.un: dest:f src1:i len:8
 unbox:
-throw: src1:i len:15
+throw: src1:i len:18
+op_rethrow: src1:i len:18
 ldfld:
 ldflda:
 stfld:
@@ -135,7 +136,7 @@ stsfld:
 stobj:
 conv.ovf.i1.un:
 conv.ovf.i2.un:
-conv.ovf.i4.un:
+conv.ovf.i4.un: dest:i src1:i len:16
 conv.ovf.i8.un:
 conv.ovf.u1.un:
 conv.ovf.u2.un:
@@ -171,11 +172,11 @@ conv.ovf.u1:
 conv.ovf.i2:
 conv.ovf.u2:
 conv.ovf.i4:
-conv.ovf.u4: dest:i src1:i len:4
+conv.ovf.u4: dest:i src1:i len:15
 conv.ovf.i8:
 conv.ovf.u8:
 refanyval:
-ckfinite: dest:f src1:f len:32
+ckfinite: dest:f src1:f len:43
 mkrefany:
 ldtoken:
 conv.u2: dest:i src1:i len:4
@@ -187,7 +188,7 @@ add.ovf:
 add.ovf.un:
 mul.ovf: dest:i src1:i src2:i clob:1 len:10
 # this opcode is handled specially in the code generator
-mul.ovf.un: dest:i src1:i src2:i len:17
+mul.ovf.un: dest:i src1:i src2:i len:18
 sub.ovf:
 sub.ovf.un:
 endfinally:
@@ -204,11 +205,11 @@ prefix2:
 prefix1:
 prefixref:
 arglist:
-ceq: dest:i len:8
-cgt: dest:i len:8
-cgt.un: dest:i len:8
-clt: dest:i len:8
-clt.un: dest:i len:8
+ceq: dest:c len:8
+cgt: dest:c len:8
+cgt.un: dest:c len:8
+clt: dest:c len:8
+clt.un: dest:c len:8
 ldftn:
 ldvirtftn:
 ldarg:
@@ -217,7 +218,7 @@ starg:
 ldloc:
 ldloca:
 stloc:
-localloc: dest:i src1:i len:74
+localloc: dest:i src1:i len:84
 endfilter:
 unaligned.:
 volatile.:
@@ -225,7 +226,6 @@ tail.:
 initobj:
 cpblk:
 initblk:
-rethrow:
 sizeof:
 refanytype:
 illegal:
@@ -243,9 +243,9 @@ rename:
 compare: src1:i src2:i len:3
 lcompare: src1:i src2:i len:3
 icompare: src1:i src2:i len:3
-compare_imm: src1:i len:7
-icompare_imm: src1:i len:7
-fcompare: src1:f src2:f clob:a len:12
+compare_imm: src1:i len:13
+icompare_imm: src1:i len:8
+fcompare: src1:f src2:f clob:a len:13
 local:
 arg:
 oparglist: src1:b len:11
@@ -253,102 +253,106 @@ outarg: src1:i len:2
 outarg_imm: len:6
 retarg:
 setret: dest:a src1:i len:3
-setlret: dest:l src1:i src2:i len:5
+setlret: dest:i src1:i src2:i len:5
 checkthis: src1:b len:5
-call: dest:a clob:c len:18
+call: dest:a clob:c len:64
 ret: len:2
-voidcall: clob:c len:18
-voidcall_reg: src1:i clob:c len:12
-voidcall_membase: src1:b clob:c len:17
-fcall: dest:f len:18 clob:c
-fcall_reg: dest:f src1:i len:12 clob:c
-fcall_membase: dest:f src1:b len:17 clob:c
-lcall: dest:l len:18 clob:c
-lcall_reg: dest:l src1:i len:12 clob:c
-lcall_membase: dest:l src1:b len:17 clob:c
-vcall: len:18 clob:c
-vcall_reg: src1:i len:12 clob:c
-vcall_membase: src1:b len:17 clob:c
-call_reg: dest:a src1:i len:12 clob:c
-call_membase: dest:a src1:b len:17 clob:c
+voidcall: clob:c len:64
+voidcall_reg: src1:i clob:c len:64
+voidcall_membase: src1:b clob:c len:64
+fcall: dest:f len:64 clob:c
+fcall_reg: dest:f src1:i len:64 clob:c
+fcall_membase: dest:f src1:b len:64 clob:c
+lcall: dest:a len:64 clob:c
+lcall_reg: dest:a src1:i len:64 clob:c
+lcall_membase: dest:a src1:b len:64 clob:c
+vcall: len:64 clob:c
+vcall_reg: src1:i len:64 clob:c
+vcall_membase: src1:b len:64 clob:c
+call_reg: dest:a src1:i len:64 clob:c
+call_membase: dest:a src1:b len:64 clob:c
 trap:
 iconst: dest:i len:10
-i8const: dest:i len:17
+i8const: dest:i len:18
 r4const: dest:f len:13
-r8const: dest:f len:13
+r8const: dest:f len:9
 regvar:
 reg:
 regoffset:
 label:
 store_membase_imm: dest:b len:15
-store_membase_reg: dest:b src1:i len:8
-storei8_membase_reg: dest:b src1:i len:8
+store_membase_reg: dest:b src1:i len:9
+storei8_membase_reg: dest:b src1:i len:9
 storei1_membase_imm: dest:b len:11
-storei1_membase_reg: dest:b src1:i len:8
-storei2_membase_imm: dest:b len:12
-storei2_membase_reg: dest:b src1:i len:8
-storei4_membase_imm: dest:b len:11
-storei4_membase_reg: dest:b src1:i len:8
-storei8_membase_imm: dest:b len:17
-storer4_membase_reg: dest:b src1:f len:8
-storer8_membase_reg: dest:b src1:f len:7
-load_membase: dest:i src1:b len:14
-loadi1_membase: dest:i src1:b len:8
-loadu1_membase: dest:i src1:b len:8
-loadi2_membase: dest:i src1:b len:8
-loadu2_membase: dest:i src1:b len:8
-loadi4_membase: dest:i src1:b len:7
-loadu4_membase: dest:i src1:b len:7
-loadi8_membase: dest:i src1:b len:17
-loadr4_membase: dest:f src1:b len:7
-loadr8_membase: dest:f src1:b len:7
+storei1_membase_reg: dest:b src1:c len:9
+storei2_membase_imm: dest:b len:13
+storei2_membase_reg: dest:b src1:i len:9
+storei4_membase_imm: dest:b len:13
+storei4_membase_reg: dest:b src1:i len:9
+storei8_membase_imm: dest:b len:18
+storer4_membase_reg: dest:b src1:f len:15
+storer8_membase_reg: dest:b src1:f len:10
+load_membase: dest:i src1:b len:15
+loadi1_membase: dest:c src1:b len:9
+loadu1_membase: dest:c src1:b len:9
+loadi2_membase: dest:i src1:b len:9
+loadu2_membase: dest:i src1:b len:9
+loadi4_membase: dest:i src1:b len:9
+loadu4_membase: dest:i src1:b len:9
+loadi8_membase: dest:i src1:b len:18
+loadr4_membase: dest:f src1:b len:16
+loadr8_membase: dest:f src1:b len:16
 loadr8_spill_membase: src1:b len:9
 loadu4_mem: dest:i len:10
+amd64_loadi8_memindex: dest:i src1:i src2:i len:10
 move: dest:i src1:i len:4
 setreg: dest:i src1:i len:4
-add_imm: dest:i src1:i len:7 clob:1
-sub_imm: dest:i src1:i len:7 clob:1
-mul_imm: dest:i src1:i len:7
+add_imm: dest:i src1:i len:8 clob:1
+sub_imm: dest:i src1:i len:8 clob:1
+mul_imm: dest:i src1:i len:8
 # there is no actual support for division or reminder by immediate
 # we simulate them, though (but we need to change the burg rules 
 # to allocate a symbolic reg for src2)
 div_imm: dest:a src1:i src2:i len:16 clob:d
 div_un_imm: dest:a src1:i src2:i len:16 clob:d
-rem_imm: dest:d src1:i src2:i len:16 clob:d
-rem_un_imm: dest:d src1:i src2:i len:16 clob:d
+rem_imm: dest:d src1:i src2:i len:16 clob:a
+rem_un_imm: dest:d src1:i src2:i len:16 clob:a
 and_imm: dest:i src1:i len:8 clob:1
 or_imm: dest:i src1:i len:8 clob:1
 xor_imm: dest:i src1:i len:8 clob:1
 shl_imm: dest:i src1:i len:8 clob:1
 shr_imm: dest:i src1:i len:8 clob:1
 shr_un_imm: dest:i src1:i len:8 clob:1
-cond_exc_eq: len:7
-cond_exc_ne_un: len:7
-cond_exc_lt: len:7
-cond_exc_lt_un: len:7
-cond_exc_gt: len:7
-cond_exc_gt_un: len:7
-cond_exc_ge: len:7
-cond_exc_ge_un: len:7
-cond_exc_le: len:7
-cond_exc_le_un: len:7
-cond_exc_ov: len:7
-cond_exc_no: len:7
-cond_exc_c: len:7
-cond_exc_nc: len:7
+cond_exc_eq: len:8
+cond_exc_ne_un: len:8
+cond_exc_lt: len:8
+cond_exc_lt_un: len:8
+cond_exc_gt: len:8
+cond_exc_gt_un: len:8
+cond_exc_ge: len:8
+cond_exc_ge_un: len:8
+cond_exc_le: len:8
+cond_exc_le_un: len:8
+cond_exc_ov: len:8
+cond_exc_no: len:8
+cond_exc_c: len:8
+cond_exc_nc: len:8
+cond_exc_iov: len:8
+cond_exc_ic: len:8
 long_add:
 long_sub:
-long_mul:
-long_div:
-long_div_un:
-long_rem:
-long_rem_un:
+long_mul: dest:i src1:i src2:i clob:1 len:4
+long_mul_imm: dest:i src1:i src2:i clob:1 len:8
+long_div: dest:a src1:a src2:i len:16 clob:d
+long_div_un: dest:a src1:a src2:i len:16 clob:d
+long_rem: dest:d src1:a src2:i len:16 clob:a
+long_rem_un: dest:d src1:a src2:i len:16 clob:a
 long_and:
 long_or:
 long_xor:
-long_shl: dest:i src1:i src2:i clob:s len:31
-long_shr: dest:i src1:i src2:i clob:s len:32
-long_shr_un: dest:i src1:i src2:i clob:s len:32
+long_shl: dest:i src1:i src2:s clob:1 len:31
+long_shr: dest:i src1:i src2:s clob:1 len:32
+long_shr_un: dest:i src1:i src2:s clob:1 len:32
 long_neg:
 long_not:
 long_conv_to_i1:
@@ -366,8 +370,8 @@ long_conv_to_ovf_i: dest:i src1:i src2:i len:40
 long_conv_to_ovf_u:
 long_add_ovf:
 long_add_ovf_un:
-long_mul_ovf: 
-long_mul_ovf_un:
+long_mul_ovf: dest:i src1:i src2:i clob:1 len:16
+long_mul_ovf_un: dest:i src1:i src2:i len:22
 long_sub_ovf:
 long_sub_ovf_un:
 long_conv_to_ovf_i1_un:
@@ -393,11 +397,11 @@ long_cgt:
 long_cgt_un:
 long_clt:
 long_clt_un:
-long_conv_to_r_un: dest:f src1:i src2:i len:47 
+long_conv_to_r_un: dest:f src1:i src2:i len:48 
 long_conv_to_u:
-long_shr_imm: dest:i src1:i len:11
-long_shr_un_imm: dest:i src1:i len:11
-long_shl_imm: dest:i src1:i len:11
+long_shr_imm: dest:i src1:i clob:1 len:11
+long_shr_un_imm: dest:i src1:i clob:1 len:11
+long_shl_imm: dest:i src1:i clob:1 len:11
 long_add_imm:
 long_sub_imm:
 long_beq:
@@ -420,14 +424,14 @@ float_bge: len:32
 float_bge_un: len:13
 float_ble: len:32
 float_ble_un: len:13
-float_add: dest:f src1:f src2:f len:3
-float_sub: dest:f src1:f src2:f len:3
-float_mul: dest:f src1:f src2:f len:3
-float_div: dest:f src1:f src2:f len:3
-float_div_un: dest:f src1:f src2:f len:3
+float_add: dest:f src1:f src2:f len:5
+float_sub: dest:f src1:f src2:f len:5
+float_mul: dest:f src1:f src2:f len:5
+float_div: dest:f src1:f src2:f len:5
+float_div_un: dest:f src1:f src2:f len:5
 float_rem: dest:f src1:f src2:f len:19
 float_rem_un: dest:f src1:f src2:f len:19
-float_neg: dest:f src1:f len:3
+float_neg: dest:f src1:f len:23
 float_not: dest:f src1:f len:3
 float_conv_to_i1: dest:i src1:f len:49
 float_conv_to_i2: dest:i src1:f len:49
@@ -468,25 +472,31 @@ float_conv_to_ovf_i8:
 float_conv_to_ovf_u8:
 float_ceq: dest:i src1:f src2:f len:35
 float_cgt: dest:i src1:f src2:f len:35
-float_cgt_un: dest:i src1:f src2:f len:47
+float_cgt_un: dest:i src1:f src2:f len:48
 float_clt: dest:i src1:f src2:f len:35
 float_clt_un: dest:i src1:f src2:f len:42
+float_ceq_membase: dest:i src1:f src2:b len:35
+float_cgt_membase: dest:i src1:f src2:b len:35
+float_cgt_un_membase: dest:i src1:f src2:b len:48
+float_clt_membase: dest:i src1:f src2:b len:35
+float_clt_un_membase: dest:i src1:f src2:b len:42
 float_conv_to_u: dest:i src1:f len:46
-call_handler: len:11
-aot_const: dest:i len:6
+fmove: dest:f src1:f len:8
+call_handler: len:14
+aot_const: dest:i len:10
 x86_test_null: src1:i len:5
-x86_compare_membase_reg: src1:b src2:i len:7
-x86_compare_membase_imm: src1:b len:12
-x86_compare_reg_membase: src1:i src2:b len:7
+x86_compare_membase_reg: src1:b src2:i len:9
+x86_compare_membase_imm: src1:b len:13
+x86_compare_reg_membase: src1:i src2:b len:8
 x86_inc_reg: dest:i src1:i clob:1 len:3
-x86_inc_membase: src1:b len:7
+x86_inc_membase: src1:b len:8
 x86_dec_reg: dest:i src1:i clob:1 len:3
-x86_dec_membase: src1:b len:7
-x86_add_membase_imm: src1:b len:12
-x86_sub_membase_imm: src1:b len:12
+x86_dec_membase: src1:b len:8
+x86_add_membase_imm: src1:b len:13
+x86_sub_membase_imm: src1:b len:13
 x86_push: src1:i len:3
 x86_push_imm: len:6
-x86_push_membase: src1:b len:7
+x86_push_membase: src1:b len:8
 x86_push_obj: src1:b len:40
 x86_lea: dest:i src1:i src2:i len:8
 x86_lea_membase: dest:i src1:i len:11
@@ -494,29 +504,38 @@ x86_xchg: src1:i src2:i clob:x len:2
 x86_fpop: src1:f len:3
 x86_fp_load_i8: dest:f src1:b len:8
 x86_fp_load_i4: dest:f src1:b len:8
-x86_seteq_membase: src1:b len:8
-x86_add_membase: dest:i src1:i src2:b clob:1 len:12
-x86_sub_membase: dest:i src1:i src2:b clob:1 len:12
+x86_seteq_membase: src1:b len:9
+x86_add_membase: dest:i src1:i src2:b clob:1 len:13
+x86_sub_membase: dest:i src1:i src2:b clob:1 len:13
 x86_mul_membase: dest:i src1:i src2:b clob:1 len:14
-amd64_icompare_membase_reg: src1:b src2:i len:7
-amd64_icompare_membase_imm: src1:b len:12
-amd64_icompare_reg_membase: src1:i src2:b len:7
-amd64_set_xmmreg: src1:f len:9
+tls_get: dest:i len:13
+amd64_test_null: src1:i len:5
+amd64_icompare_membase_reg: src1:b src2:i len:8
+amd64_icompare_membase_imm: src1:b len:13
+amd64_icompare_reg_membase: src1:i src2:b len:8
+amd64_set_xmmreg_r4: dest:f src1:f len:14 clob:m
+amd64_set_xmmreg_r8: dest:f src1:f len:14 clob:m
+atomic_add_i4: src1:b src2:i dest:i len:32
+atomic_add_new_i4: src1:b src2:i dest:i len:32
+atomic_exchange_i4: src1:b src2:i dest:i len:32
+atomic_add_i8: src1:b src2:i dest:i len:32
+atomic_add_new_i8: src1:b src2:i dest:i len:32
+atomic_exchange_i8: src1:b src2:i dest:i len:32
 adc: dest:i src1:i src2:i len:3 clob:1
 addcc: dest:i src1:i src2:i len:3 clob:1
 subcc: dest:i src1:i src2:i len:3 clob:1
-adc_imm: dest:i src1:i len:7 clob:1
+adc_imm: dest:i src1:i len:8 clob:1
 sbb: dest:i src1:i src2:i len:3 clob:1
-sbb_imm: dest:i src1:i len:7 clob:1
+sbb_imm: dest:i src1:i len:8 clob:1
 br_reg: src1:i len:3
-sin: dest:f src1:f len:7
-cos: dest:f src1:f len:7
-abs: dest:f src1:f len:3
+sin: dest:f src1:f len:32
+cos: dest:f src1:f len:32
+abs: dest:f src1:f len:32
 tan: dest:f src1:f len:59
 atan: dest:f src1:f len:9
-sqrt: dest:f src1:f len:3
-op_bigmul: len:3 dest:l src1:a src2:i
-op_bigmul_un: len:3 dest:l src1:a src2:i
+sqrt: dest:f src1:f len:32
+op_bigmul: len:3 dest:i src1:a src2:i
+op_bigmul_un: len:3 dest:i src1:a src2:i
 sext_i1: dest:i src1:i len:4
 sext_i2: dest:i src1:i len:4
 
@@ -527,16 +546,16 @@ int_sub: dest:i src1:i src2:i clob:1 len:64
 int_mul: dest:i src1:i src2:i clob:1 len:64
 int_mul_ovf: dest:i src1:i src2:i clob:1 len:64
 int_mul_ovf_un: dest:i src1:i src2:i clob:1 len:64
-int_div: dest:a src1:i src2:i clob:d len:64
-int_div_un: dest:a src1:i src2:i clob:d len:64
-int_rem: dest:d src1:i src2:i clob:d len:64
-int_rem_un: dest:d src1:i src2:i clob:d len:64
+int_div: dest:a src1:a src2:i clob:d len:64
+int_div_un: dest:a src1:a src2:i clob:d len:64
+int_rem: dest:d src1:a src2:i clob:a len:64
+int_rem_un: dest:d src1:a src2:i clob:a len:64
 int_and: dest:i src1:i src2:i clob:1 len:64
 int_or: dest:i src1:i src2:i clob:1 len:64
 int_xor: dest:i src1:i src2:i clob:1 len:64
-int_shl: dest:i src1:i src2:i clob:s len:64
-int_shr: dest:i src1:i src2:i clob:s len:64
-int_shr_un: dest:i src1:i src2:i clob:s len:64
+int_shl: dest:i src1:i src2:s clob:1 len:64
+int_shr: dest:i src1:i src2:s clob:1 len:64
+int_shr_un: dest:i src1:i src2:s clob:1 len:64
 int_adc: dest:i src1:i src2:i clob:1 len:64
 int_adc_imm: dest:i src1:i clob:1 len:64
 int_sbb: dest:i src1:i src2:i clob:1 len:64
@@ -548,8 +567,8 @@ int_sub_imm: dest:i src1:i clob:1 len:64
 int_mul_imm: dest:i src1:i clob:1 len:64
 int_div_imm: dest:a src1:i clob:d len:64
 int_div_un_imm: dest:a src1:i clob:d len:64
-int_rem_imm: dest:d src1:i clob:d len:64
-int_rem_un_imm: dest:d src1:i clob:d len:64
+int_rem_imm: dest:d src1:i clob:a len:64
+int_rem_un_imm: dest:d src1:i clob:a len:64
 int_and_imm: dest:i src1:i clob:1 len:64
 int_or_imm: dest:i src1:i clob:1 len:64
 int_xor_imm: dest:i src1:i clob:1 len:64
@@ -558,11 +577,11 @@ int_shr_imm: dest:i src1:i clob:1 len:64
 int_shr_un_imm: dest:i src1:i clob:1 len:64
 int_neg: dest:i src1:i clob:1 len:64
 int_not: dest:i src1:i clob:1 len:64
-int_ceq: dest:i len:64
-int_cgt: dest:i len:64
-int_cgt_un: dest:i len:64
-int_clt: dest:i len:64
-int_clt_un: dest:i len:64
+int_ceq: dest:c len:64
+int_cgt: dest:c len:64
+int_cgt_un: dest:c len:64
+int_clt: dest:c len:64
+int_clt_un: dest:c len:64
 int_beq: len:64
 int_bne_un: len:64
 int_blt: len:64