+
# x86-class cpu description file
# this file is read by genmdesc to pruduce a table with all the relevant information
# about the cpu instructions that may be used by the regsiter allocator, the scheduler
tailcall: len:120 clob:c
br: len:6
label: len:0
-seq_point: len:25
+seq_point: len:31
long_add: dest:i src1:i src2:i len:3 clob:1 nacl:6
long_sub: dest:i src1:i src2:i len:3 clob:1 nacl:6
move: dest:i src1:i len:3
add_imm: dest:i src1:i len:8 clob:1 nacl:11
sub_imm: dest:i src1:i len:8 clob:1 nacl:11
-mul_imm: dest:i src1:i len:11
+mul_imm: dest:i src1:i len:12
and_imm: dest:i src1:i len:8 clob:1
or_imm: dest:i src1:i len:8 clob:1
xor_imm: dest:i src1:i len:8 clob:1
amd64_set_xmmreg_r8: dest:f src1:f len:14 clob:m
amd64_save_sp_to_lmf: len:16
tls_get: dest:i len:16
+tls_get_reg: dest:i src1:i len:20
atomic_add_i4: src1:b src2:i dest:i len:32
atomic_add_new_i4: src1:b src2:i dest:i len:32
atomic_exchange_i4: src1:b src2:i dest:a len:32
sext_i2: dest:i src1:i len:4
sext_i4: dest:i src1:i len:8
+laddcc: dest:i src1:i src2:i len:3 clob:1
+lsubcc: dest:i src1:i src2:i len:3 clob:1
+
# 32 bit opcodes
int_add: dest:i src1:i src2:i clob:1 len:4 nacl:7
int_sub: dest:i src1:i src2:i clob:1 len:4 nacl:7
int_ble: len:8
int_ble_un: len:8
-card_table_wbarrier: src1:a src2:i clob:d len:42
+card_table_wbarrier: src1:a src2:i clob:d len:56
relaxed_nop: len:2
hard_nop: len:1
pshufflew_high: dest:x src1:x len:6
pshufflew_low: dest:x src1:x len:6
pshuffled: dest:x src1:x len:6
+shufps: dest:x src1:x src2:x len:5 clob:1
+shufpd: dest:x src1:x src2:x len:6 clob:1
extract_mask: dest:i src1:x len:6
pshlq: dest:x src1:x len:6 clob:1
pshlq_reg: dest:x src1:x src2:x len:5 clob:1
+cvtdq2pd: dest:x src1:x len:5 clob:1
+cvtdq2ps: dest:x src1:x len:4 clob:1
+cvtpd2dq: dest:x src1:x len:5 clob:1
+cvtpd2ps: dest:x src1:x len:5 clob:1
+cvtps2dq: dest:x src1:x len:5 clob:1
+cvtps2pd: dest:x src1:x len:4 clob:1
+cvttpd2dq: dest:x src1:x len:5 clob:1
+cvttps2dq: dest:x src1:x len:5 clob:1
+
xmove: dest:x src1:x len:5
xzero: dest:x len:5
liverange_start: len:0
liverange_end: len:0
+gc_liveness_def: len:0
+gc_liveness_use: len:0
+gc_spill_slot_liveness_def: len:0
+gc_param_slot_liveness_def: len:0
+