First set of licensing changes

[mono.git] / mono / arch / x86 / x86-codegen.h

diff --git a/mono/arch/x86/x86-codegen.h b/mono/arch/x86/x86-codegen.h
index 0c67b45d56879658e25e3f15acc3be429b1e4597..6c9d63f37e991fc8cbaeedf8ce4fd635695253c3 100644 (file)
--- a/mono/arch/x86/x86-codegen.h
+++ b/mono/arch/x86/x86-codegen.h
@@ -10,6 +10,7 @@
  * 
  * Copyright (C)  2000 Intel Corporation.  All rights reserved.
  * Copyright (C)  2001, 2002 Ximian, Inc.
+ * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  */
 
 #ifndef X86_H
@@ -522,8 +523,17 @@ typedef union {
 
 #endif /* __native_client_codegen__ */
 
+#define x86_mfence(inst) \
+       do {    \
+               x86_codegen_pre(&(inst), 3); \
+               *(inst)++ = 0x0f;       \
+               *(inst)++ = 0xae;       \
+               *(inst)++ = 0xf0;       \
+       } while (0)
+
 #define x86_rdtsc(inst) \
        do {    \
+               x86_codegen_pre(&(inst), 2); \
                *(inst)++ = 0x0f;       \
                *(inst)++ = 0x31;       \
        } while (0)
@@ -584,7 +594,7 @@ typedef union {
 
 #define x86_xadd_reg_reg(inst,dreg,reg,size)   \
        do {    \
-               x86_codegen_pre(&(inst), 4); \
+               x86_codegen_pre(&(inst), 3); \
                *(inst)++ = (unsigned char)0x0F;     \
                if ((size) == 1)        \
                        *(inst)++ = (unsigned char)0xC0;        \
@@ -670,14 +680,14 @@ typedef union {
 
 #define x86_neg_mem(inst,mem)  \
        do {    \
-               x86_codegen_pre(&(inst), 2); \
+               x86_codegen_pre(&(inst), 6); \
                *(inst)++ = (unsigned char)0xf7;        \
                x86_mem_emit ((inst), 3, (mem));        \
        } while (0)
 
 #define x86_neg_membase(inst,basereg,disp)     \
        do {    \
-               x86_codegen_pre(&(inst), 6); \
+               x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
                *(inst)++ = (unsigned char)0xf7;        \
                x86_membase_emit ((inst), 3, (basereg), (disp));        \
        } while (0)
@@ -813,6 +823,14 @@ typedef union {
                x86_imm_emit32 ((inst), (imm)); \
        } while (0)
 
+#define x86_test_mem_imm8(inst,mem,imm)        \
+       do {    \
+               x86_codegen_pre(&(inst), 7); \
+               *(inst)++ = (unsigned char)0xf6;        \
+               x86_mem_emit ((inst), 0, (mem));        \
+               x86_imm_emit8 ((inst), (imm));  \
+       } while (0)
+
 #define x86_test_mem_imm(inst,mem,imm) \
        do {    \
                x86_codegen_pre(&(inst), 10); \
@@ -881,11 +899,11 @@ typedef union {
 #define x86_shift_membase_imm(inst,opc,basereg,disp,imm)       \
        do {    \
                if ((imm) == 1) {       \
-                       x86_codegen_pre(&(inst), 6); \
+                       x86_codegen_pre(&(inst), 1 + kMaxMembaseEmitPadding); \
                        *(inst)++ = (unsigned char)0xd1;        \
                        x86_membase_emit ((inst), (opc), (basereg), (disp));    \
                } else {        \
-                       x86_codegen_pre(&(inst), 7); \
+                       x86_codegen_pre(&(inst), 2 + kMaxMembaseEmitPadding); \
                        *(inst)++ = (unsigned char)0xc1;        \
                        x86_membase_emit ((inst), (opc), (basereg), (disp));    \
                        x86_imm_emit8 ((inst), (imm));  \
@@ -1030,7 +1048,7 @@ typedef union {
                } else {        \
                        x86_codegen_pre(&(inst), 6); \
                        *(inst)++ = (unsigned char)0x69;        \
-                       x86_reg_emit ((inst), (reg), (mem));    \
+                       x86_mem_emit ((inst), (reg), (mem));    \
                        x86_imm_emit32 ((inst), (imm)); \
                }       \
        } while (0)
@@ -2382,7 +2400,15 @@ typedef enum {
        X86_SSE_PEXTRD = 0x16,/*sse41*/
 
        X86_SSE_SHUFP = 0xC6,   
-       
+
+       X86_SSE_CVTDQ2PD = 0xE6,
+       X86_SSE_CVTDQ2PS = 0x5B,
+       X86_SSE_CVTPD2DQ = 0xE6,
+       X86_SSE_CVTPD2PS = 0x5A,
+       X86_SSE_CVTPS2DQ = 0x5B,
+       X86_SSE_CVTPS2PD = 0x5A,
+       X86_SSE_CVTTPD2DQ = 0xE6,
+       X86_SSE_CVTTPS2DQ = 0x5B,
 } X86_SSE_Opcode;