First set of licensing changes

[mono.git] / mono / arch / mips / mips-codegen.h

diff --git a/mono/arch/mips/mips-codegen.h b/mono/arch/mips/mips-codegen.h
index adb3200cb70d0d73cbb500247d67bb65925c820a..c579c88a9b3a990a26afc0edaeac0c2da8693417 100644 (file)
--- a/mono/arch/mips/mips-codegen.h
+++ b/mono/arch/mips/mips-codegen.h
@@ -4,6 +4,7 @@
  * Copyright (c) 2004 Novell, Inc
  * Author: Paolo Molaro (lupus@ximian.com)
  *
+ * Licensed under the MIT license. See LICENSE file in the project root for full license information.
  */
 
 /* registers */
@@ -16,6 +17,7 @@ enum {
        mips_a1,
        mips_a2,
        mips_a3,
+#if _MIPS_SIM == _ABIO32
        mips_t0, /* 8 temporaries */
        mips_t1,
        mips_t2,
@@ -24,6 +26,16 @@ enum {
        mips_t5,
        mips_t6,
        mips_t7,
+#elif _MIPS_SIM == _ABIN32
+       mips_a4, /* 4 more argument registers */
+       mips_a5,
+       mips_a6,
+       mips_a7,
+       mips_t0, /* 4 temporaries */
+       mips_t1,
+       mips_t2,
+       mips_t3,
+#endif
        mips_s0, /* 16 calle saved */
        mips_s1,
        mips_s2,
@@ -148,6 +160,30 @@ enum {
        MIPS_FPU_NGT
 };
 
+#if SIZEOF_REGISTER == 4
+
+#define MIPS_SW                mips_sw
+#define MIPS_LW                mips_lw
+#define MIPS_ADDU      mips_addu
+#define MIPS_ADDIU     mips_addiu
+#define MIPS_SWC1      mips_swc1
+#define MIPS_LWC1      mips_lwc1
+#define MIPS_MOVE      mips_move
+
+#elif SIZEOF_REGISTER == 8
+
+#define MIPS_SW                mips_sd
+#define MIPS_LW                mips_ld
+#define MIPS_ADDU      mips_daddu
+#define MIPS_ADDIU     mips_daddiu
+#define MIPS_SWC1      mips_sdc1
+#define MIPS_LWC1      mips_ldc1
+#define MIPS_MOVE      mips_dmove
+
+#else
+#error Unknown SIZEOF_REGISTER
+#endif
+
 #define mips_emit32(c,x) do {                          \
                *((guint32 *) (void *)(c)) = x;                         \
                (c) = (typeof(c))(((guint32 *)(void *)(c)) + 1);        \
@@ -158,21 +194,17 @@ enum {
 #define mips_format_r(code,op,rs,rt,rd,sa,func) mips_emit32 ((code), (((op)<<26)|((rs)<<21)|((rt)<<16)|((rd)<<11)|((sa)<<6)|(func)))
 #define mips_format_divmul(code,op,src1,src2,fun) mips_emit32 ((code), (((op)<<26)|((src1)<<21)|((src2)<<16)|(fun)))
 
-#define mips_is_imm16(val) ((gint)(val) >= (gint)-(1<<15) && (gint)(val) <= (gint)((1<<15)-1))
+#define mips_is_imm16(val) ((gint)(gshort)(gint)(val) == (gint)(val))
 
 /* Load always using lui/addiu pair (for later patching) */
 #define mips_load(c,D,v) do {  \
-               if (!mips_is_imm16 ((v)))       {       \
-                       if (((guint32)(v)) & (1 << 15)) {               \
-                               mips_lui ((c), (D), mips_zero, (((guint32)(v))>>16)+1); \
-                       } \
-                       else {                  \
-                               mips_lui ((c), (D), mips_zero, (((guint32)(v))>>16)); \
-                       }                                               \
-                       mips_addiu ((c), (D), (D), ((guint32)(v)) & 0xffff); \
-               }                                                       \
-               else                                                    \
-                       mips_addiu ((c), (D), mips_zero, ((guint32)(v)) & 0xffff); \
+               if (((guint32)(v)) & (1 << 15)) {                                                               \
+                       mips_lui ((c), (D), mips_zero, (((guint32)(v))>>16)+1);         \
+               }                                                                                                                               \
+               else {                                                                                                                  \
+                       mips_lui ((c), (D), mips_zero, (((guint32)(v))>>16));           \
+               }                                                                                                                               \
+               mips_addiu ((c), (D), (D), ((guint32)(v)) & 0xffff);                    \
        } while (0)
 
 /* load constant - no patch-up */
@@ -301,8 +333,9 @@ enum {
 #define mips_swr(c,src,base,offset) mips_format_i(c,54,base,src,offset)
 
 /* misc and coprocessor ops */
-#define mips_move(c,dest,src) mips_add(c,dest,src,mips_zero)
-#define mips_nop(c) mips_sll(c,0,0,0)
+#define mips_move(c,dest,src) mips_addu(c,dest,src,mips_zero)
+#define mips_dmove(c,dest,src) mips_daddu(c,dest,src,mips_zero)
+#define mips_nop(c) mips_or(c,mips_at,mips_at,0)
 #define mips_break(c,code) mips_emit32(c, ((code)<<6)|13)
 #define mips_mfhi(c,dest) mips_format_r(c,0,0,0,dest,0,16)
 #define mips_mflo(c,dest) mips_format_r(c,0,0,0,dest,0,18)