Merge pull request #2819 from BrzVlad/fix-major-log

[mono.git] / mono / arch / arm / arm-vfp-codegen.h

diff --git a/mono/arch/arm/arm-vfp-codegen.h b/mono/arch/arm/arm-vfp-codegen.h
index e1f760b440cd884ed28c7da72cce570287a028d0..edf558da2995f17b8e5663b0a4656bfc76576ec9 100644 (file)
--- a/mono/arch/arm/arm-vfp-codegen.h
+++ b/mono/arch/arm/arm-vfp-codegen.h
@@ -1,10 +1,15 @@
+//
+// Copyright 2011 Xamarin Inc
+//
+// Licensed under the MIT license. See LICENSE file in the project root for full license information.
+
 #ifndef __MONO_ARM_VFP_CODEGEN_H__
 #define __MONO_ARM_VFP_CODEGEN_H__
 
 #include "arm-codegen.h"
 
 enum {
-       /* FPA registers */
+       /* VFP registers */
        ARM_VFP_F0,
        ARM_VFP_F1,
        ARM_VFP_F2,
@@ -112,7 +117,7 @@ enum {
 
 #define ARM_DEF_VFP_LSF(cond,cp,post,ls,wback,basereg,Fd,offset)       \
        ((offset) >= 0? (offset)>>2: -(offset)>>2)      |       \
-       ((6 << 25)                                      |       \
+       (6 << 25)                                       |       \
        ((cp) << 8)                                     |       \
        (((Fd) >> 1) << 12)                             |       \
        (((Fd) & 1) << 22)                              |       \
@@ -156,9 +161,20 @@ enum {
 #define ARM_FSTD(p,freg,base,offset)   \
        ARM_FSTD_COND(p,freg,base,offset,ARMCOND_AL)
 
-#include "arm_vfpmacros.h"
+#define ARM_FLDMD_COND(p,first_reg,nregs,base,cond)                                                    \
+       ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_DOUBLE,0,ARMOP_LDR,0,(base),(first_reg),((nregs) * 2) << 2))
+
+#define ARM_FLDMD(p,first_reg,nregs,base)              \
+       ARM_FLDMD_COND(p,first_reg,nregs,base,ARMCOND_AL)
+
+#define ARM_FSTMD_COND(p,first_reg,nregs,base,cond)                                                    \
+       ARM_EMIT((p), ARM_DEF_VFP_LSF((cond),ARM_VFP_COPROC_DOUBLE,0,ARMOP_STR,0,(base),(first_reg),((nregs) * 2) << 2))
+
+#define ARM_FSTMD(p,first_reg,nregs,base)              \
+       ARM_FSTMD_COND(p,first_reg,nregs,base,ARMCOND_AL)
+
+#include <mono/arch/arm/arm_vfpmacros.h>
 
-#define ARM_DEF_VFP_CPT(cond,cp,op,L,Fn,Rd)
 /* coprocessor register transfer */
 #define ARM_FMSR(p,freg,reg)   \
        ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_SINGLE,0,0,(freg),(reg)))
@@ -176,8 +192,57 @@ enum {
 
 #define ARM_FMXR(p,freg,reg)   \
        ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_SINGLE,7,0,(freg),(reg)))
-#define ARM_FMRX(p,reg,freg)   \
-       ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_SINGLE,7,1,(freg),(reg)))
+#define ARM_FMRX(p,reg,fcreg)  \
+       ARM_EMIT((p), ARM_DEF_VFP_CPT(ARMCOND_AL,ARM_VFP_COPROC_SINGLE,7,1,(fcreg),(reg)))
+
+#define ARM_FMSTAT(p)   \
+       ARM_FMRX((p),ARMREG_R15,ARM_VFP_SCR)
+
+#define ARM_DEF_MCRR(cond,cp,rn,rd,Fm,M) \
+       ((Fm) << 0) |                                      \
+       (1 << 4)   |                                       \
+       ((M) << 5) |                                       \
+       ((cp) << 8) |                                      \
+       ((rd) << 12) |                                     \
+       ((rn) << 16) |                                     \
+       ((2) << 21) |                                      \
+       (12 << 24) |                                       \
+       ARM_DEF_COND(cond)
+
+#define ARM_FMDRR(p,rd,rn,dm)   \
+       ARM_EMIT((p), ARM_DEF_MCRR(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,(rn),(rd),(dm) >> 1, (dm) & 1))
+
+#define ARM_DEF_FMRRD(cond,cp,rn,rd,Dm,D)              \
+       ((Dm) << 0) |                                      \
+       (1 << 4)   |                                       \
+       ((cp) << 8) |                                      \
+       ((rd) << 12) |                                     \
+       ((rn) << 16) |                                     \
+       ((0xc5) << 20) |                                           \
+       ARM_DEF_COND(cond)
+
+#define ARM_FMRRD(p,rd,rn,dm)   \
+       ARM_EMIT((p), ARM_DEF_FMRRD(ARMCOND_AL,ARM_VFP_COPROC_DOUBLE,(rn),(rd),(dm) >> 1, (dm) & 1))
+
+#define ARM_DEF_FUITOS(cond,Dd,D,Fm,M) ((cond) << 28) | ((0x1d) << 23) | ((D) << 22) | ((0x3) << 20) | ((8) << 16) | ((Dd) << 12) | ((0xa) << 8) | ((1) << 6) | ((M) << 5) | ((Fm) << 0)
+
+#define ARM_FUITOS(p,dreg,sreg) \
+       ARM_EMIT((p), ARM_DEF_FUITOS (ARMCOND_AL, (dreg) >> 1, (dreg) & 1, (sreg) >> 1, (sreg) & 1))
+
+#define ARM_DEF_FUITOD(cond,Dd,D,Fm,M) ((cond) << 28) | ((0x1d) << 23) | ((D) << 22) | ((0x3) << 20) | ((8) << 16) | ((Dd) << 12) | ((0xb) << 8) | ((1) << 6) | ((M) << 5) | ((Fm) << 0)
+
+#define ARM_FUITOD(p,dreg,sreg) \
+       ARM_EMIT((p), ARM_DEF_FUITOD (ARMCOND_AL, (dreg) >> 1, (dreg) & 1, (sreg) >> 1, (sreg) & 1))
+
+#define ARM_DEF_FSITOS(cond,Dd,D,Fm,M) ((cond) << 28) | ((0x1d) << 23) | ((D) << 22) | ((0x3) << 20) | ((8) << 16) | ((Dd) << 12) | ((0xa) << 8) | ((1) << 7) | ((1) << 6) | ((M) << 5) | ((Fm) << 0)
+
+#define ARM_FSITOS(p,dreg,sreg) \
+       ARM_EMIT((p), ARM_DEF_FSITOS (ARMCOND_AL, (dreg) >> 1, (dreg) & 1, (sreg) >> 1, (sreg) & 1))
+
+#define ARM_DEF_FSITOD(cond,Dd,D,Fm,M) ((cond) << 28) | ((0x1d) << 23) | ((D) << 22) | ((0x3) << 20) | ((8) << 16) | ((Dd) << 12) | ((0xb) << 8) | ((1) << 7) | ((1) << 6) | ((M) << 5) | ((Fm) << 0)
+
+#define ARM_FSITOD(p,dreg,sreg) \
+       ARM_EMIT((p), ARM_DEF_FSITOD (ARMCOND_AL, (dreg) >> 1, (dreg) & 1, (sreg) >> 1, (sreg) & 1))
 
 #endif /* __MONO_ARM_VFP_CODEGEN_H__ */