7seg small changes

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 7cf1548ff4c59000d9b0a12c864fabbbad7570ec..8c13049009229ccac1826458c1ae41d9df3b989c 100644 (file)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -8,6 +8,7 @@ use work.core_pkg.all;
 use work.mem_pkg.all;
 use work.extension_pkg.all;
 use work.extension_uart_pkg.all;
+use work.extension_7seg_pkg.all;
 
 architecture behav of writeback_stage is
 
@@ -16,9 +17,9 @@ signal data_addr : word_t;
 
 signal wb_reg, wb_reg_nxt : writeback_rec;
 
-signal ext_uart,ext_timer,ext_gpmp :  extmod_rec;
+signal ext_uart,ext_timer,ext_gpmp,ext_7seg :  extmod_rec;
 
-signal sel_nxt :std_logic;
+signal sel_nxt, dmem_we, bus_rx :std_logic;
 
 
 
@@ -35,7 +36,7 @@ begin
                        clk,
                        data_addr(DATA_ADDR_WIDTH+1 downto 2),
                        data_addr(DATA_ADDR_WIDTH+1 downto 2),
-                       wb_reg_nxt.dmem_write_en,
+                       dmem_we,
                        ram_data,
                        data_ram_read
                );
@@ -49,9 +50,23 @@ uart : extension_uart
                        reset,
                        ext_uart,
                        data_ram_read_ext,
+                       bus_rx,
                        bus_tx
                );
-
+       
+sseg : extension_7seg
+       generic map(
+               RESET_VALUE
+               )
+       port map(
+               clk,
+               reset,
+               ext_7seg,
+               sseg0,
+               sseg1,
+               sseg2,
+               sseg3
+               );
        
 syn: process(clk, reset)
 
@@ -63,8 +78,10 @@ begin
                wb_reg.dmem_write_en <= '0';
                wb_reg.hword <= '0';
                wb_reg.byte_s <= '0';
+               bus_rx <= '1';
        elsif rising_edge(clk) then
                wb_reg <= wb_reg_nxt;
+               bus_rx <= '1';
        end if;
        
 end process; 
@@ -149,9 +166,11 @@ begin
        reg_addr <= result_addr;
 
        data_addr <= (others => '0');
+       dmem_we <= '0';
        
-       if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) = '1') then
+       if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
                data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
+               dmem_we <= wb_reg_nxt.dmem_write_en;
        end if;
 end process;
 
@@ -159,12 +178,18 @@ end process;
 addr_de_mult: process(wb_reg_nxt.address, ram_data, wb_reg,sel_nxt,wb_reg_nxt.dmem_write_en)
 
 begin
-               ext_uart.sel <='0';
+  ext_uart.sel <='0';
   ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
   ext_uart.byte_en <= (others => '0');
   ext_uart.data <= (others => '0');
   ext_uart.addr <= (others => '0');
 
+  ext_7seg.sel <='0';
+  ext_7seg.wr_en <= wb_reg_nxt.dmem_write_en;
+  ext_7seg.byte_en <= (others => '0');
+  ext_7seg.data <= (others => '0');
+  ext_7seg.addr <= (others => '0');
+  
   ext_timer.sel <='0';
   ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
   ext_timer.byte_en <= (others => '0');
@@ -176,14 +201,14 @@ begin
   ext_gpmp.byte_en <= (others => '0');
   ext_gpmp.data <= (others => '0');
   ext_gpmp.addr <= (others => '0');
-                                                 -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
- case wb_reg_nxt.address(wb_reg_nxt.address'high downto 4) is
+   -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
+ case wb_reg_nxt.address(31 downto 4) is
        when EXT_UART_ADDR => 
                ext_uart.sel <='1';
-               ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
+               ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
                ext_uart.data <= ram_data;
-               ext_uart.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
-               case wb_reg.address(1 downto 0) is
+               ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
+               case wb_reg_nxt.address(1 downto 0) is
                                when "00" => ext_uart.byte_en <= "0001";
                                when "01" => ext_uart.byte_en <= "0010";
                                when "10" => ext_uart.byte_en <= "0100";
@@ -191,6 +216,23 @@ begin
                                when "11" => ext_uart.byte_en <= "1111";
                                when others => null;
                        end case;
+
+       when EXT_7SEG_ADDR => 
+               ext_7seg.sel <='1';
+               ext_7seg.wr_en <= wb_reg_nxt.dmem_write_en;
+               ext_7seg.data <= ram_data;
+               ext_7seg.addr <= wb_reg_nxt.address(31 downto 2);
+               ext_7seg.byte_en(1 downto 0) <= wb_reg_nxt.address(1 downto 0);
+
+               
+--             case wb_reg_nxt.address(1 downto 0) is
+--                     when "00" => ext_7seg.byte_en <= "0001";
+--                     when "01" => ext_7seg.byte_en <= "0010";
+--                     when "10" => ext_7seg.byte_en <= "0100";
+--                     when "11" => ext_7seg.byte_en <= "1000";
+--                     when others => null;
+--             end case;
+                       
        when EXT_TIMER_ADDR => 
                ext_timer.sel <='1';
                ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;