7seg small changes

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 5123f76a76bfb08c59ce09e0609667181e326d2b..8c13049009229ccac1826458c1ae41d9df3b989c 100644 (file)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -7,14 +7,19 @@ use work.core_pkg.all;
 
 use work.mem_pkg.all;
 use work.extension_pkg.all;
+use work.extension_uart_pkg.all;
+use work.extension_7seg_pkg.all;
 
 architecture behav of writeback_stage is
 
-signal data_ram_read : word_t;
+signal data_ram_read, data_ram_read_ext : word_t;
+signal data_addr : word_t;
 
 signal wb_reg, wb_reg_nxt : writeback_rec;
 
-signal ext_uart,ext_timer,ext_gpmp :  extmod_rec;
+signal ext_uart,ext_timer,ext_gpmp,ext_7seg :  extmod_rec;
+
+signal sel_nxt, dmem_we, bus_rx :std_logic;
 
 
 
@@ -29,13 +34,39 @@ begin
                
                port map (
                        clk,
-                       wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
-                       wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
-                       wb_reg_nxt.dmem_write_en,
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       dmem_we,
                        ram_data,
                        data_ram_read
                );
 
+uart : extension_uart 
+       generic map(
+               RESET_VALUE
+               )
+       port map(
+                       clk ,
+                       reset,
+                       ext_uart,
+                       data_ram_read_ext,
+                       bus_rx,
+                       bus_tx
+               );
+       
+sseg : extension_7seg
+       generic map(
+               RESET_VALUE
+               )
+       port map(
+               clk,
+               reset,
+               ext_7seg,
+               sseg0,
+               sseg1,
+               sseg2,
+               sseg3
+               );
        
 syn: process(clk, reset)
 
@@ -47,8 +78,10 @@ begin
                wb_reg.dmem_write_en <= '0';
                wb_reg.hword <= '0';
                wb_reg.byte_s <= '0';
+               bus_rx <= '1';
        elsif rising_edge(clk) then
                wb_reg <= wb_reg_nxt;
+               bus_rx <= '1';
        end if;
        
 end process; 
@@ -62,7 +95,7 @@ end process;
 
 
 
-shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred)
+shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en)
 
 begin
        wb_reg_nxt.address <= address;
@@ -126,49 +159,80 @@ end process;
 
 
 
-out_logic: process(write_en, result_addr, wb_reg, alu_jmp)
+out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt)
 
 begin  
        reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
        reg_addr <= result_addr;
+
+       data_addr <= (others => '0');
+       dmem_we <= '0';
+       
+       if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
+               data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
+               dmem_we <= wb_reg_nxt.dmem_write_en;
+       end if;
 end process;
 
 
-addr_de_mult: process(wb_reg_nxt.address, ram_data, wb_reg)
+addr_de_mult: process(wb_reg_nxt.address, ram_data, wb_reg,sel_nxt,wb_reg_nxt.dmem_write_en)
 
 begin
-
   ext_uart.sel <='0';
-  ext_uart.wr_en <= '0';
+  ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
   ext_uart.byte_en <= (others => '0');
   ext_uart.data <= (others => '0');
   ext_uart.addr <= (others => '0');
 
+  ext_7seg.sel <='0';
+  ext_7seg.wr_en <= wb_reg_nxt.dmem_write_en;
+  ext_7seg.byte_en <= (others => '0');
+  ext_7seg.data <= (others => '0');
+  ext_7seg.addr <= (others => '0');
+  
   ext_timer.sel <='0';
-  ext_timer.wr_en <= '0';
+  ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
   ext_timer.byte_en <= (others => '0');
   ext_timer.data <= (others => '0');
   ext_timer.addr <= (others => '0');
 
   ext_gpmp.sel <='0';
-  ext_gpmp.wr_en <= '0';
+  ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
   ext_gpmp.byte_en <= (others => '0');
   ext_gpmp.data <= (others => '0');
   ext_gpmp.addr <= (others => '0');
-                                                 -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
- case wb_reg_nxt.address(wb_reg_nxt.address'high downto 4) is
+   -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
+ case wb_reg_nxt.address(31 downto 4) is
        when EXT_UART_ADDR => 
-               ext_uart.sel <='1';
-               ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
+               ext_uart.sel <='1';
+               ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
                ext_uart.data <= ram_data;
-               ext_uart.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
-               case wb_reg.address(1 downto 0) is
+               ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
+               case wb_reg_nxt.address(1 downto 0) is
                                when "00" => ext_uart.byte_en <= "0001";
                                when "01" => ext_uart.byte_en <= "0010";
                                when "10" => ext_uart.byte_en <= "0100";
-                               when "11" => ext_uart.byte_en <= "1000";
+                               --when "11" => ext_uart.byte_en <= "1000";
+                               when "11" => ext_uart.byte_en <= "1111";
                                when others => null;
                        end case;
+
+       when EXT_7SEG_ADDR => 
+               ext_7seg.sel <='1';
+               ext_7seg.wr_en <= wb_reg_nxt.dmem_write_en;
+               ext_7seg.data <= ram_data;
+               ext_7seg.addr <= wb_reg_nxt.address(31 downto 2);
+               ext_7seg.byte_en(1 downto 0) <= wb_reg_nxt.address(1 downto 0);
+
+               
+--             case wb_reg_nxt.address(1 downto 0) is
+--                     when "00" => ext_7seg.byte_en <= "0001";
+--                     when "01" => ext_7seg.byte_en <= "0010";
+--                     when "10" => ext_7seg.byte_en <= "0100";
+--                     when "11" => ext_7seg.byte_en <= "1000";
+--                     when others => null;
+--             end case;
+                       
        when EXT_TIMER_ADDR => 
                ext_timer.sel <='1';
                ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;