instruction memory progammer: is in and works in simulations

[calu.git] / cpu / src / writeback_stage.vhd

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 9a5657d5fca82cd497346e12fc672af8e22a0358..aacba01de09a655846e40b1ba7b08d0b92ffbf10 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -34,7 +34,22 @@ entity writeback_stage is
                        reg_we : out std_logic;
                        reg_addr : out gp_addr_t;
                        jump_addr : out instruction_addr_t;
-                       jump : out std_logic
+                       jump : out std_logic;
+                       -- hallo stefan mir adden da jetzt mal schnell an uart port :D
+                       bus_tx : out std_logic;
+                       bus_rx : in std_logic;
+                       -- instruction memory program port :D
+                       new_im_data_out : out std_logic;
+                       im_addr : out gp_register_t;
+                       im_data : out gp_register_t;
+                       
+                       sseg0 : out std_logic_vector(0 to 6);
+                       sseg1 : out std_logic_vector(0 to 6);
+                       sseg2 : out std_logic_vector(0 to 6);
+                       sseg3 : out std_logic_vector(0 to 6);
+
+                       int_req : out interrupt_t
+
                );
                
 end writeback_stage;