instr mem durch case, fibonacci als programm, 7seg als extension geadded, resultat...

[calu.git] / cpu / src / writeback_stage.vhd

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 9a5657d5fca82cd497346e12fc672af8e22a0358..73c5df43499e1401bc04a496f9cc5b941d0cab4a 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -34,7 +34,14 @@ entity writeback_stage is
                        reg_we : out std_logic;
                        reg_addr : out gp_addr_t;
                        jump_addr : out instruction_addr_t;
-                       jump : out std_logic
+                       jump : out std_logic;
+                       -- hallo stefan mir adden da jetzt mal schnell an uart port :D
+                       bus_tx : out std_logic;
+                       
+                       sseg0 : out std_logic_vector(0 to 6);
+                       sseg1 : out std_logic_vector(0 to 6);
+                       sseg2 : out std_logic_vector(0 to 6);
+                       sseg3 : out std_logic_vector(0 to 6)
                );
                
 end writeback_stage;