instr mem durch case, fibonacci als programm, 7seg als extension geadded, resultat...

[calu.git] / cpu / src / writeback_stage.vhd

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 7d6e3c2abe68ba3c671af34ebc2e0b711782cd10..73c5df43499e1401bc04a496f9cc5b941d0cab4a 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -2,13 +2,15 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
+use work.common_pkg.all;
+
 entity writeback_stage is
 
        generic (
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       LOGIC_ACT : std_logic
                        
                        );
        port(
@@ -22,7 +24,7 @@ entity writeback_stage is
                        ram_data : in word_t;           --ureg
                        alu_jmp : in std_logic;         --reg
                        br_pred : in std_logic;         --reg
-                       write_en : in std_logic;        --reg  (register file)
+                       write_en : in std_logic;        --reg  (register file) bei jump 1 wenn addr in result
                        dmem_en : in std_logic;         --ureg (jump addr in mem or in address)
                        dmem_write_en : in std_logic;   --ureg
                        hword : in std_logic;           --ureg
@@ -32,7 +34,14 @@ entity writeback_stage is
                        reg_we : out std_logic;
                        reg_addr : out gp_addr_t;
                        jump_addr : out instruction_addr_t;
-                       jump : out std_logic
+                       jump : out std_logic;
+                       -- hallo stefan mir adden da jetzt mal schnell an uart port :D
+                       bus_tx : out std_logic;
+                       
+                       sseg0 : out std_logic_vector(0 to 6);
+                       sseg1 : out std_logic_vector(0 to 6);
+                       sseg2 : out std_logic_vector(0 to 6);
+                       sseg3 : out std_logic_vector(0 to 6)
                );
                
 end writeback_stage;