ram_data : in word_t; --ureg
alu_jmp : in std_logic; --reg
br_pred : in std_logic; --reg
- write_en : in std_logic; --reg (register file)
+ write_en : in std_logic; --reg (register file) bei jump 1 wenn addr in result
dmem_en : in std_logic; --ureg (jump addr in mem or in address)
dmem_write_en : in std_logic; --ureg
hword : in std_logic; --ureg
reg_we : out std_logic;
reg_addr : out gp_addr_t;
jump_addr : out instruction_addr_t;
- jump : out std_logic
+ jump : out std_logic;
+ -- hallo stefan mir adden da jetzt mal schnell an uart port :D
+ bus_tx : out std_logic;
+
+ sseg0 : out std_logic_vector(0 to 6);
+ sseg1 : out std_logic_vector(0 to 6);
+ sseg2 : out std_logic_vector(0 to 6);
+ sseg3 : out std_logic_vector(0 to 6)
);
end writeback_stage;