instr mem durch case, fibonacci als programm, 7seg als extension geadded, resultat...

[calu.git] / cpu / src / r_w_ram_b.vhd

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 3664ea109adc72d064b8d5dedf146f016eee0683..e735c203e428d8429ad454e54fff09d9798bb59b 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -10,22 +10,20 @@ architecture behaviour of r_w_ram is
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE := (0 => "11100000000000011001000000000000",  -- r0 = r3 + r2 (always)
-                                 1 => "11100101000000001000100000000010",  -- r0 = r1 << 0 (always)
-                                 2 => "11100000000010000001100000000000",  -- r1 = r0 + r3 (always)
-                                 3 => "11100000101000000001000000000000",
-                                 4 => "11100001000110010111011001101100", 
-                                 others => x"E0000000");
-
+       signal ram : RAM_TYPE;
+       
 begin
        process(clk)
        begin
                if rising_edge(clk) then
-                       data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+                data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+
+
                        
                        if wr_en = '1' then
                                ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
                        end if;
                end if;
        end process;
+       
 end architecture behaviour;