instr mem durch case, fibonacci als programm, 7seg als extension geadded, resultat...

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index 0f1949504fd3f8c59361ffa5b24d169ef15871eb..8539c425f568c71fc42d6381affabb26a14fd5e9 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -4,6 +4,7 @@ use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.core_pkg.all;
+use work.extension_pkg.all;
 -------------------------------------------------------------------------------
 -- ENTITY
 -------------------------------------------------------------------------------
@@ -30,6 +31,7 @@ architecture behavior of pipeline_tb is
                signal branch_prediction_bit_pin : std_logic;
                signal alu_jump_bit_pin : std_logic;
                signal instruction_pin : instruction_word_t;
+               signal prog_cnt : instruction_addr_t;
 
                signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                signal reg_wr_data_pin : gp_register_t;
@@ -46,9 +48,17 @@ architecture behavior of pipeline_tb is
                  signal dmem_pin  : std_logic;--memop
                  signal dmem_wr_en_pin : std_logic;
                  signal hword_pin  : std_logic;
-                 signal byte_s_pin : std_logic;
+                 signal byte_s_pin, tx_pin : std_logic;
+                                
+                                 signal gpm_in_pin : extmod_rec;
+                                signal gpm_out_pin : gp_register_t;
                 signal nop_pin : std_logic;
 
+                signal cycle_cnt : integer;
+
+               signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
+
+
 begin
 
 --             instruction_ram : r_w_ram
@@ -85,8 +95,9 @@ begin
                        alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
 
                --Data outputs
-                       instruction => instruction_pin --: out instruction_word_t
-               );
+                       instruction => instruction_pin, --: out instruction_word_t
+                       prog_cnt => prog_cnt
+               );      
 
        decode_st : decode_stage
                generic map (
@@ -103,6 +114,7 @@ begin
 
                --Data inputs
                        instruction => instruction_pin, --: in instruction_word_t;
+                       prog_cnt => prog_cnt,
                        reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                        reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
                        reg_we => reg_we_pin, --: in std_logic;
@@ -116,17 +128,19 @@ begin
                );
           exec_st : execute_stage
                 generic map('0')
-                port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin, result_pin, result_addr_pin,addr_pin,
-                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
+                port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
           writeback_st : writeback_stage
                 generic map('0', '1')
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, sseg0, sseg1, sseg2, sseg3);
+
+
 
 
-       nop_pin <= (alu_jump_bit_pin xor brpr_pin);
+       nop_pin <= (alu_jump_bit_pin);-- xor brpr_pin);
 
 -------------------------------------------------------------------------------
 -- generate simulation clock
@@ -139,6 +153,18 @@ begin
     wait for cc/2;
   end process CLKGEN;
   
+
+  cnt : process(sys_clk_pin, sys_res_n_pin)
+
+  begin
+
+       if (sys_res_n_pin = '0') then
+               cycle_cnt <= 0;
+       elsif (sys_clk_pin'event and sys_clk_pin = '1') then
+               cycle_cnt <= cycle_cnt + 1;
+       end if;
+
+  end process cnt;
 -------------------------------------------------------------------------------
 -- test the design
 -------------------------------------------------------------------------------
@@ -167,7 +193,7 @@ begin
        wait until sys_res_n_pin = '1';
        
 
-       icwait(100000);
+       icwait(1000000000);
 
     ---------------------------------------------------------------------------
     -- exit testbench