instruction memory progammer: is in and works in simulations

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index d87cee18d26c4f271b2cc9e479f89c26840b2d72..0bdcaca896d5b82b17fbbe6bd911ecbdec7fe861 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -18,8 +18,10 @@ end pipeline_tb;
 -------------------------------------------------------------------------------
 architecture behavior of pipeline_tb is
 
-       constant cc : time := 30 ns;        -- test clock period
-       
+       constant cc : time := 20 ns;        -- test clock period
+       constant SYS_CLOCK_FREQ : integer := 50000000;
+       constant BAUD_COUNT : integer := SYS_CLOCK_FREQ/115200;
+
                signal sys_clk_pin : std_logic;
                signal sys_res_n_pin : std_logic;
                --Data input
@@ -48,7 +50,7 @@ architecture behavior of pipeline_tb is
                  signal dmem_pin  : std_logic;--memop
                  signal dmem_wr_en_pin : std_logic;
                  signal hword_pin  : std_logic;
-                 signal byte_s_pin : std_logic;
+                 signal byte_s_pin, tx_pin, rx_pin : std_logic;
                                 
                                  signal gpm_in_pin : extmod_rec;
                                 signal gpm_out_pin : gp_register_t;
@@ -56,6 +58,11 @@ architecture behavior of pipeline_tb is
 
                 signal cycle_cnt : integer;
 
+               signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
+               signal int_req_pin : interrupt_t;
+
+               signal new_im_data :std_logic;
+               signal im_addr, im_data : gp_register_t;
 
 begin
 
@@ -91,10 +98,14 @@ begin
                        prediction_result => prediction_result_pin, --: in instruction_addr_t;
                        branch_prediction_bit => branch_prediction_bit_pin,  --: in std_logic;
                        alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+                       new_im_data_in => new_im_data,
+                       im_addr => im_addr,
+                       im_data => im_data,
 
                --Data outputs
                        instruction => instruction_pin, --: out instruction_word_t
-                       prog_cnt => prog_cnt
+                       prog_cnt => prog_cnt,
+                       int_req => int_req_pin
                );      
 
        decode_st : decode_stage
@@ -133,7 +144,7 @@ begin
                 generic map('0', '1')
                 port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);
 
 
 
@@ -175,6 +186,17 @@ begin
         wait until sys_clk_pin = '1' and sys_clk_pin'event;
       end loop;
     end;
+
+       procedure txd(trans_data : in std_logic_vector) is
+       begin
+               for i in 0 to 9 loop
+                       rx_pin <= trans_data(i);
+                       dummy <= not dummy;
+                       wait on dummy;
+                       icwait(BAUD_COUNT);
+               end loop;
+       end txd;
+
        
   begin
     -----------------------------------------------------------------------------
@@ -190,6 +212,9 @@ begin
        sys_res_n_pin <= '1';
        wait until sys_res_n_pin = '1';
        
+       icwait(10);
+
+       txd("0100000101");
 
        icwait(1000000000);