port map (
clk,
- instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
+ im_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
- instr_we,
- instr_wr_data,
+ new_im_data_in,
+ im_data,
instr_rd_data
);
if (reset = RESET_VALUE) then
instr_r_addr <= (others => '0');
- rom_ram <= ROM_USE;
+ rom_ram <= ROM_USE;
+ led2 <= '0';
elsif rising_edge(clk) then
instr_r_addr <= instr_r_addr_nxt;
rom_ram <= rom_ram_nxt;
+ led2 <= rom_ram; --rom_ram_nxt;
end if;
end process;
-asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
-
+asyn: process(reset, s_reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
+variable instr_pc : instruction_addr_t;
begin
rom_ram_nxt <= rom_ram;
-
+
case rom_ram is
when ROM_USE =>
instruction <= instr_rd_data_rom;
when others =>
instruction <= x"F0000000";
end case;
- instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
+ instr_pc := std_logic_vector(unsigned(instr_r_addr) + 1);
+ instr_r_addr_nxt <= instr_pc;
- if (instr_r_addr(ROM_INSTR_ADDR_WIDTH) = '1' and rom_ram = ROM_USE) then
+ if (instr_pc = x"0000007f" and rom_ram = ROM_USE) then
rom_ram_nxt <= RAM_USE;
- instr_r_addr_nxt <= (others => '0');
+ -- TODO: wenn genau auf adresse 0 im RAM ein br steht kracht es... :/
+ instr_r_addr_nxt <= x"00000000";
end if;
-
+
if (reset = RESET_VALUE) then
instr_r_addr_nxt <= (others => '0');
end if;
when others => null;
end case;
+ if (s_reset = RESET_VALUE) then
+ rom_ram_nxt <= RAM_USE;
+ instr_r_addr_nxt <= (others => '0');
+ end if;
+
end process;
out_logic : process (instr_r_addr, alu_jump_bit, int_req, jump_result)