ldih/l

[calu.git] / cpu / src / fetch_stage_b.vhd

diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd
index 67dde3cc764e392975ca730a19f9f76ad68f1130..5a3f7556519938a35505fe158adb0e2d178b8fc0 100644 (file)
--- a/cpu/src/fetch_stage_b.vhd
+++ b/cpu/src/fetch_stage_b.vhd
@@ -17,7 +17,7 @@ signal instr_rd_data   : instruction_word_t;
 
 begin
 
-       instruction_ram : r_w_ram
+       instruction_ram : rom --r_w_ram --rom
                generic map (
                        PHYS_INSTR_ADDR_WIDTH,
                        WORD_WIDTH
@@ -57,12 +57,16 @@ begin
        end if;
 
        if (alu_jump_bit = LOGIC_ACT) then
-               instr_r_addr_nxt <= jump_result;        
+               instr_r_addr_nxt <= jump_result;
+               instruction(31 downto 28) <= "1111";    
        elsif (branch_prediction_bit = LOGIC_ACT) then
                instr_r_addr_nxt <= prediction_result;
        end if; 
 
 end process;
 
+prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
+prog_cnt(31 downto 11) <= (others => '0');
+
 end behav;