static branch incl prediction rc1

[calu.git] / cpu / src / execute_stage_b.vhd

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index 5979a8b048b917574ddc48f5ac5a6efb3ee51e2f..a7809e51786d9deb457f0458de37d3c2b74e1448 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -5,6 +5,7 @@ use IEEE.numeric_std.all;
 use work.common_pkg.all;
 use work.alu_pkg.all;
 use work.gpm_pkg.all;
+use work.extension_pkg.all;
 
 architecture behav of execute_stage is
 
@@ -14,6 +15,11 @@ signal op_detail : op_opt_t;
 signal left_operand, right_operand : gp_register_t;
 signal alu_state, alu_nxt : alu_result_rec;
 signal psw : status_rec;
+               -- extension signals
+               signal ext_gpmp :  extmod_rec;
+               signal data_out    : gp_register_t;
+
+
 
 type exec_internal is record
         result : gp_register_t;
@@ -29,11 +35,23 @@ begin
 
 alu_inst : alu
 port map(clk, reset, condition, op_group, 
-         left_operand, right_operand, op_detail, alu_state, alu_nxt,addr,data);
+         left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, alu_nxt,addr,data);
+
+
+
+       gpmp_inst :  extension_gpm
+               generic map (RESET_VALUE)
+               port map (
+                       clk,
+                       reset,
+                       ext_gpmp,
+                       data_out,
+                       alu_nxt,
+                       psw
+                       
+               );
+
 
-gpm_inst : gpm
-        generic map(RESET_VALUE)
-        port map(clk,reset,alu_nxt,psw);
 
 syn: process(clk, reset)
 
@@ -51,17 +69,16 @@ begin
        
 end process;
 
-asyn: process(reset,dec_instr, alu_nxt, psw, reg)
+asyn: process(reset,dec_instr, alu_nxt, psw, reg,left_operand,right_operand)
 begin
 
         condition <= dec_instr.condition;
         op_group <= dec_instr.op_group;
         op_detail <= dec_instr.op_detail;
-        left_operand <= dec_instr.src1;
-        right_operand <= dec_instr.src2;
+        
 
 
-        alu_state <= (reg.result,dec_instr.daddr,psw,'0',dec_instr.brpr,'0','0','0','0','0','0'); 
+        alu_state <= (reg.result,dec_instr.daddr,psw,reg.alu_jump,reg.brpr,'0','0','0','0','0','0'); 
         
 
         if reset = RESET_VALUE then
@@ -78,15 +95,37 @@ begin
 
 end process asyn;
 
+forward: process(regfile_val, reg_we, reg_addr, dec_instr)
+begin
+       left_operand <= dec_instr.src1;
+        right_operand <= dec_instr.src2;
+
+       if reg_we = '1' then
+               if dec_instr.saddr1 = reg_addr then
+                       left_operand <= regfile_val;
+               end if;
+               if (dec_instr.saddr2 = reg_addr)  and  (dec_instr.op_detail(IMM_OPT) = '0') then
+                       right_operand <= regfile_val;
+               end if;
+       end if;
+end process forward;
+
 result <= reg.result;
 result_addr <= reg.res_addr;
 alu_jump <= reg.alu_jump;
 brpr <= reg.brpr;
 wr_en <= reg.wr_en;
 dmem <= alu_nxt.mem_op;
+--dmem <= reg.result(4);
 dmem_write_en <= alu_nxt.mem_en;
+--dmem_write_en <= reg.result(0);
+--dmem_write_en <= '1';
 hword <= alu_nxt.hw_op;
+--hword <= reg.result(1);
 byte_s <= alu_nxt.byte_op;
 
+--addr <= alu_nxt.result;
+--data <= right_operand;
+--byte_s <= reg.result(2);
 end behav;