instr mem durch case, fibonacci als programm, 7seg als extension geadded, resultat...

[calu.git] / cpu / src / decoder_b.vhd

diff --git a/cpu/src/decoder_b.vhd b/cpu/src/decoder_b.vhd
index 01c11f07b82393499d2f094f7677825b52158672..7425381c64162eede4c65b665c5f70338c67e4a7 100644 (file)
--- a/cpu/src/decoder_b.vhd
+++ b/cpu/src/decoder_b.vhd
@@ -154,7 +154,7 @@ begin
                instr_s.op_detail(IMM_OPT) := '1';
                instr_s.op_detail(NO_PSW_OPT) := instruction(0);
 
-               if (instr_s.opcode = "00111") then
+               if (instr_s.opcode = "00101") then
                        instr_s.op_group := AND_OP;
                end if;
 
@@ -217,10 +217,15 @@ begin
                instr_s.reg_src1_addr := instruction(18 downto 15);
                instr_s.signext := instruction(2);
                instr_s.high_low := instruction(1);
+               instr_s.displacement(14 downto 0) := instruction(14 downto 0);
 
                instr_s.op_group := LDST_OP;
                instr_s.op_detail(NO_PSW_OPT) := '1';
 
+               if (instr_s.displacement(14) = '1') then
+                       instr_s.displacement(31 downto 15) := (others => '1');
+               end if;
+
                if (instr_s.opcode = "11010") then              --ldi
                        if (instr_s.high_low = '1') then
                                instr_s.immediate(31 downto 16) := instruction(18 downto 3);
@@ -275,6 +280,10 @@ begin
                instr_s.op_detail(NO_PSW_OPT) := '1';
                 instr_s.op_detail(ST_OPT) := '1';
                instr_s.op_group := LDST_OP;
+
+               if (instr_s.displacement(14) = '1') then
+                       instr_s.displacement(31 downto 15) := (others => '1');
+               end if;
        end if;
 
 --     when "10001" =>         --sth