static branch incl prediction rc1

[calu.git] / cpu / src / decode_stage_b.vhd

diff --git a/cpu/src/decode_stage_b.vhd b/cpu/src/decode_stage_b.vhd
index 7d42e8fdf9f56a829512f8072e8e163d331bdcad..dc5e389b7527bf11aad11cbd5580728b0a08669a 100644 (file)
--- a/cpu/src/decode_stage_b.vhd
+++ b/cpu/src/decode_stage_b.vhd
@@ -66,7 +66,8 @@ begin
                dec_op_inst.saddr1 <= (others => '0');
                dec_op_inst.saddr2 <= (others => '0');
                dec_op_inst.daddr <= (others => '0');
-
+               dec_op_inst.displacement <= (others => '0');
+               dec_op_inst.prog_cnt <= (others => '0');
 
        elsif rising_edge(clk) then
                rtw_rec <= rtw_rec_nxt;
@@ -92,7 +93,7 @@ end process;
 --     end record;
 
 -- output logic incl. bypassing reg-file
-output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data)
+output_next_stage: process(dec_op_inst, reg1_rd_data, reg2_rd_data, nop)
 
 begin
 
@@ -100,6 +101,10 @@ begin
        to_next_stage.src1 <= reg1_rd_data;
        to_next_stage.src2 <= reg2_rd_data;
 
+       if (nop = '1') then
+               to_next_stage.condition <= "1111";
+       end if;
+
 end process;
 
 
@@ -116,6 +121,8 @@ begin
        dec_op_inst_nxt.saddr2 <= instr_spl.reg_src2_addr;
        dec_op_inst_nxt.daddr <= instr_spl.reg_dest_addr; --(others => '0');
        dec_op_inst_nxt.op_group <= instr_spl.op_group;
+       dec_op_inst_nxt.displacement <= instr_spl.displacement;
+       dec_op_inst_nxt.prog_cnt <= prog_cnt;
 
 end process;
 
@@ -152,6 +159,7 @@ begin
        rtw_rec_nxt.rtw_reg2 <= '0';
        rtw_rec_nxt.immediate <= (others => '0');
        rtw_rec_nxt.imm_set <= '0';
+--- ???? wieso
        rtw_rec_nxt.reg1_addr <= instr_spl.reg_src1_addr;
        rtw_rec_nxt.reg2_addr <= instr_spl.reg_src2_addr;
 
@@ -164,7 +172,7 @@ begin
                rtw_rec_nxt.rtw_reg1 <= ('1' and reg_we);
        end if;
 
-       if (reg_w_addr = instr_spl.reg_src1_addr) then
+       if (reg_w_addr = instr_spl.reg_src2_addr) then
                rtw_rec_nxt.rtw_reg2 <= ('1' and reg_we);
        end if;
 
@@ -180,7 +188,7 @@ begin
        branch_prediction_bit <= '0';
 
        if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
-               branch_prediction_res <= instr_spl.immediate;   --both 32 bit
+               branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt));  --both 32 bit
                branch_prediction_bit <= '1';
        end if;