instr mem durch case, fibonacci als programm, 7seg als extension geadded, resultat...

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index d67243c4f9e2ae16d4302c47cbe5a7892af6d3ef..d81095c664d43b01cdaa528d893979df97c91434 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -4,23 +4,30 @@ use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.core_pkg.all;
+use work.extension_pkg.all;
 
 entity core_top is
 
        port(
                --System input pins
+                  sys_res : in std_logic;
                        sys_clk : in std_logic;
-                       sys_res : in std_logic;
-                       result : out gp_register_t;
-                       jump_result : out instruction_addr_t;
-                       reg_wr_data : out gp_register_t
+--                     result : out gp_register_t;
+--                     reg_wr_data : out gp_register_t
+                 -- uart
+                       bus_tx : out std_logic;
                        
+                       sseg0 : out std_logic_vector(0 to 6);
+                       sseg1 : out std_logic_vector(0 to 6);
+                       sseg2 : out std_logic_vector(0 to 6);
+                       sseg3 : out std_logic_vector(0 to 6)
                );
 
 end core_top;
 
 architecture behav of core_top is
 
+               signal jump_result : instruction_addr_t;
                signal jump_result_pin : instruction_addr_t;
                signal prediction_result_pin : instruction_addr_t;
                signal branch_prediction_bit_pin : std_logic;
@@ -48,8 +55,8 @@ architecture behav of core_top is
                  signal hword_pin  : std_logic;
                  signal byte_s_pin : std_logic;
                                 
-                                signal gpm_in_pin : ext_mod_rec;
-                                signal gpm_out_pin : gp_register_t;
+                signal gpm_in_pin : extmod_rec;
+                signal gpm_out_pin : gp_register_t;
                 signal nop_pin : std_logic;
 
 
@@ -114,7 +121,7 @@ begin
                 generic map('0', '1')
                 port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
 
 
 
@@ -131,10 +138,11 @@ begin
        
 --end process;
        
-       result <= result_pin;
+--     result <= result_pin;
        nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
 
-       jump_result <= jump_result_pin;
+       jump_result <= prog_cnt_pin; --jump_result_pin;
+--     sys_res <= '1';
 
-       reg_wr_data <= reg_wr_data_pin;
+--     reg_wr_data <= reg_wr_data_pin;
 end behav;