ldih/l

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index d81095c664d43b01cdaa528d893979df97c91434..14c04c382aa483d59ed24908373b27496eb8f95b 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -10,12 +10,13 @@ entity core_top is
 
        port(
                --System input pins
-                  sys_res : in std_logic;
+                  sys_res_unsync : in std_logic;
                        sys_clk : in std_logic;
 --                     result : out gp_register_t;
 --                     reg_wr_data : out gp_register_t
                  -- uart
                        bus_tx : out std_logic;
+                       bus_rx : in std_logic;
                        
                        sseg0 : out std_logic_vector(0 to 6);
                        sseg1 : out std_logic_vector(0 to 6);
@@ -27,6 +28,9 @@ end core_top;
 
 architecture behav of core_top is
 
+               constant SYNC_STAGES : integer := 2;
+               constant RESET_VALUE : std_logic := '0';
+
                signal jump_result : instruction_addr_t;
                signal jump_result_pin : instruction_addr_t;
                signal prediction_result_pin : instruction_addr_t;
@@ -58,8 +62,12 @@ architecture behav of core_top is
                 signal gpm_in_pin : extmod_rec;
                 signal gpm_out_pin : gp_register_t;
                 signal nop_pin : std_logic;
+                
+                signal sys_res : std_logic;
 
+                signal vers, vers_nxt : exec2wb_rec;
 
+                signal sync : std_logic_vector(1 to SYNC_STAGES);
 begin
 
        fetch_st : fetch_stage
@@ -117,15 +125,63 @@ begin
                 port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
-          writeback_st : writeback_stage
+
+                       vers_nxt.result <= result_pin;
+                       vers_nxt.result_addr <= result_addr_pin;
+                       vers_nxt.address <= addr_pin;
+                       vers_nxt.ram_data <= data_pin;
+                       vers_nxt.alu_jmp <= alu_jump_pin;
+                       vers_nxt.br_pred <= brpr_pin;
+                       vers_nxt.write_en <= wr_en_pin;
+                       vers_nxt.dmem_en <= dmem_pin;
+                       vers_nxt.dmem_write_en <= dmem_wr_en_pin;
+                       vers_nxt.hword <= hword_pin;
+                       vers_nxt.byte_s <= byte_s_pin;
+                                                                        
+--          writeback_st : writeback_stage
+--                generic map('0', '1')
+--                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
+--                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+--                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
+--
+
+                       writeback_st : writeback_stage
                 generic map('0', '1')
-                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
-                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
+                port map(sys_clk, sys_res, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
+                vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3);
 
 
+syn: process(sys_clk, sys_res)
+
+begin
 
+       if sys_res = '0' then
+                       vers.result <= (others => '0');
+                       vers.result_addr <= (others => '0');
+                       vers.address <= (others => '0');
+                       vers.ram_data <= (others => '0');
+                       vers.alu_jmp <= '0';
+                       vers.br_pred <= '0';
+                       vers.write_en <= '0';
+                       vers.dmem_en <= '0';
+                       vers.dmem_write_en <= '0';
+                       vers.hword <= '0';
+                       vers.byte_s <= '0';
+                       sync <= (others => '0');
+       elsif rising_edge(sys_clk) then
+               vers <= vers_nxt;
+               
+               sync(1) <= sys_res_unsync xor RESET_VALUE;
+               for i in 2 to SYNC_STAGES loop
+                       sync(i) <= sync(i - 1);
+               end loop;
+               
+       end if;
+       
+end process;
 
+sys_res <= sync(SYNC_STAGES);
                
 --init : process(all)
 
@@ -145,4 +201,5 @@ begin
 --     sys_res <= '1';
 
 --     reg_wr_data <= reg_wr_data_pin;
+
 end behav;