ldih/l

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index 5352332ddcc9744162ed4eaefa41bf07ea3bdc04..14c04c382aa483d59ed24908373b27496eb8f95b 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -10,12 +10,13 @@ entity core_top is
 
        port(
                --System input pins
-                  sys_res : in std_logic;
+                  sys_res_unsync : in std_logic;
                        sys_clk : in std_logic;
 --                     result : out gp_register_t;
 --                     reg_wr_data : out gp_register_t
                  -- uart
                        bus_tx : out std_logic;
+                       bus_rx : in std_logic;
                        
                        sseg0 : out std_logic_vector(0 to 6);
                        sseg1 : out std_logic_vector(0 to 6);
@@ -27,6 +28,9 @@ end core_top;
 
 architecture behav of core_top is
 
+               constant SYNC_STAGES : integer := 2;
+               constant RESET_VALUE : std_logic := '0';
+
                signal jump_result : instruction_addr_t;
                signal jump_result_pin : instruction_addr_t;
                signal prediction_result_pin : instruction_addr_t;
@@ -58,9 +62,12 @@ architecture behav of core_top is
                 signal gpm_in_pin : extmod_rec;
                 signal gpm_out_pin : gp_register_t;
                 signal nop_pin : std_logic;
+                
+                signal sys_res : std_logic;
 
                 signal vers, vers_nxt : exec2wb_rec;
 
+                signal sync : std_logic_vector(1 to SYNC_STAGES);
 begin
 
        fetch_st : fetch_stage
@@ -140,9 +147,9 @@ begin
 
                        writeback_st : writeback_stage
                 generic map('0', '1')
-                port map(sys_clk, sys_res, vers.result, vers.result_addr, vers.address, vers.ram_data, vers.alu_jmp, vers.br_pred, 
-                vers.write_en, vers.dmem_en, vers.dmem_write_en, vers.hword, vers.byte_s,
-                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
+                port map(sys_clk, sys_res, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
+                vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, sseg0, sseg1, sseg2, sseg3);
 
 
 syn: process(sys_clk, sys_res)
@@ -161,12 +168,20 @@ begin
                        vers.dmem_write_en <= '0';
                        vers.hword <= '0';
                        vers.byte_s <= '0';
+                       sync <= (others => '0');
        elsif rising_edge(sys_clk) then
                vers <= vers_nxt;
+               
+               sync(1) <= sys_res_unsync xor RESET_VALUE;
+               for i in 2 to SYNC_STAGES loop
+                       sync(i) <= sync(i - 1);
+               end loop;
+               
        end if;
        
 end process;
 
+sys_res <= sync(SYNC_STAGES);
                
 --init : process(all)