fmax incr

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index 7ec0743961062e2158db09df3d6cbbe669e657e8..1002989d03e2fcbca282ee82d7e221219f24bc14 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -4,6 +4,7 @@ use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.core_pkg.all;
+use work.extension_pkg.all;
 
 entity core_top is
 
@@ -11,8 +12,9 @@ entity core_top is
                --System input pins
                        sys_clk : in std_logic;
                        sys_res : in std_logic;
-
-                       to_next_stage : out dec_op
+--                     result : out gp_register_t;
+                       jump_result : out instruction_addr_t
+--                     reg_wr_data : out gp_register_t
                        
                );
 
@@ -25,14 +27,32 @@ architecture behav of core_top is
                signal branch_prediction_bit_pin : std_logic;
                signal alu_jump_bit_pin : std_logic;
                signal instruction_pin : instruction_word_t;
+               signal prog_cnt_pin : instruction_addr_t;
 
                signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                signal reg_wr_data_pin : gp_register_t;
                signal reg_we_pin : std_logic;
+               signal to_next_stage : dec_op;
 
 --             signal reg1_rd_data_pin : gp_register_t;
 --             signal reg2_rd_data_pin : gp_register_t;
 
+                 signal result_pin : gp_register_t;--reg
+                 signal result_addr_pin : gp_addr_t;--reg
+                 signal addr_pin : word_t; --memaddr
+                 signal data_pin : gp_register_t; --mem data --ureg
+                 signal alu_jump_pin : std_logic;--reg
+                 signal brpr_pin  : std_logic;  --reg
+                 signal wr_en_pin : std_logic;--regop --reg
+                 signal dmem_pin  : std_logic;--memop
+                 signal dmem_wr_en_pin : std_logic;
+                 signal hword_pin  : std_logic;
+                 signal byte_s_pin : std_logic;
+                                
+                signal gpm_in_pin : extmod_rec;
+                signal gpm_out_pin : gp_register_t;
+                signal nop_pin : std_logic;
+
 
 begin
 
@@ -55,7 +75,8 @@ begin
                        alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
 
                --Data outputs
-                       instruction => instruction_pin --: out instruction_word_t
+                       instruction => instruction_pin, --: out instruction_word_t
+                       prog_cnt => prog_cnt_pin                
                );
 
        decode_st : decode_stage
@@ -73,9 +94,11 @@ begin
 
                --Data inputs
                        instruction => instruction_pin, --: in instruction_word_t;
+                       prog_cnt => prog_cnt_pin,
                        reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                        reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
                        reg_we => reg_we_pin, --: in std_logic;
+                       nop => nop_pin,
 
                --Data outputs
                        branch_prediction_res => prediction_result_pin, --: instruction_word_t;
@@ -83,17 +106,36 @@ begin
                        to_next_stage => to_next_stage
                );
 
+          exec_st : execute_stage
+                generic map('0')
+                port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
+
+          writeback_st : writeback_stage
+                generic map('0', '1')
+                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
+                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+
+
+
+
                
 --init : process(all)
 
 --begin
-       jump_result_pin <= (others => '0');
-       alu_jump_bit_pin <= '0';
-       reg_w_addr_pin <= (others => '0');
-       reg_wr_data_pin <= (others => '0');
-       reg_we_pin <= '0';
+--     jump_result_pin <= (others => '0');
+--     alu_jump_bit_pin <= '0';
+--     reg_w_addr_pin <= (others => '0');
+--     reg_wr_data_pin <= (others => '0');
+--     reg_we_pin <= '0';
        
 --end process;
        
+--     result <= result_pin;
+       nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
+
+       jump_result <= prog_cnt_pin; --jump_result_pin;
 
+--     reg_wr_data <= reg_wr_data_pin;
 end behav;