subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0);
+ subtype instr_addr_t is instruction_addr_t;
subtype gp_addr_t is std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
subtype data_ram_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
constant ARITH_OPT : integer := 1;
constant CARRY_OPT : integer := 2;
-
+
constant RIGHT_OPT : integer := 3;
+ constant JMP_REG_OPT : integer := 3;
+ constant ST_OPT : integer := 3;
constant NO_PSW_OPT : integer := 4;--no sharing
constant NO_DST_OPT : integer := 5; --no sharing
- type op_info_t is (ADDSUB_OP,AND_OP,OR_OP, XOR_OP,SHIFT_OP, LDST_OP);
+ type op_info_t is (ADDSUB_OP,AND_OP,OR_OP, XOR_OP,SHIFT_OP, LDST_OP, JMP_OP, JMP_ST_OP);
subtype op_opt_t is std_logic_vector(NUM_OP_OPT_WIDTH-1 downto 0);
immediate : std_logic_vector(WORD_WIDTH-1 downto 0);
+ displacement : gp_register_t;
+
jmptype : std_logic_vector(1 downto 0);
high_low, fill, signext, bp: std_logic;
op_group : op_info_t;
op_detail : op_opt_t;
brpr : std_logic;
+
+ displacement : gp_register_t;
+ prog_cnt : instr_addr_t;
src1 : gp_register_t;
src2 : gp_register_t;