added: alu jumps

[calu.git] / cpu / src / alu_b.vhd

diff --git a/cpu/src/alu_b.vhd b/cpu/src/alu_b.vhd
index 511b15426f36e640b167936aea137bc07290dd9c..8399d6087e835d11d1375fc5a43e4c7d5bf10c27 100755 (executable)
--- a/cpu/src/alu_b.vhd
+++ b/cpu/src/alu_b.vhd
@@ -21,36 +21,50 @@ architecture behaviour of alu is
        );                      \r
        end component exec_op;\r
        \r
-       signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;\r
+       signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;
+        signal left, right : gp_register_t;\r
        \r
 begin\r
 \r
-       add_inst : exec_op\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, add_result);\r
+       add_inst : entity work.exec_op(add_op)\r
+       port map(clk,reset,left, right, op_detail, alu_state, add_result);\r
        \r
-       and_inst : exec_op\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, and_result);\r
-       or_inst : exec_op\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, or_result);\r
-       xor_inst : exec_op\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, xor_result);\r
+       and_inst : entity work.exec_op(and_op)\r
+       port map(clk,reset,left, right, op_detail, alu_state, and_result);\r
+\r
+       or_inst : entity work.exec_op(or_op)\r
+       port map(clk,reset,left, right, op_detail, alu_state, or_result);\r
+\r
+       xor_inst : entity work.exec_op(xor_op)\r
+       port map(clk,reset,left, right, op_detail, alu_state, xor_result);\r
        \r
-       shift_inst : exec_op\r
-       port map(clk,reset,left_operand, right_operand, op_detail, alu_state, shift_result);\r
+       shift_inst : entity work.exec_op(shift_op)\r
+       port map(clk,reset,left, right, op_detail, alu_state, shift_result);\r
 \r
-calc: process(condition, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result)\r
        variable result_v : alu_result_rec;\r
        variable res_prod : std_logic;\r
        variable cond_met : std_logic;\r
-       variable mem_en : std_logic;\r
+       variable mem_en : std_logic;
+        variable mem_op : std_logic;
+       variable alu_jmp : std_logic;\r
 begin\r
        result_v := alu_state;\r
        \r
-       result_v.result := add_result.result;\r
        res_prod := '1';\r
-       mem_en := '0';\r
-       \r
-       case condition is\r
+       mem_en := '0';
+        mem_op := '0';
+       alu_jump := '0';\r
+  
+        left <= left_operand;
+        right <= right_operand;
+
+        addr <= add_result.result;
+        data <= right_operand;\r
+       
+       result_v.result := add_result.result;
+\r
+       case cond is\r
        when COND_NZERO =>\r
                cond_met := not(alu_state.status.zero);\r
        when COND_ZERO =>\r
@@ -83,8 +97,11 @@ begin
                cond_met := '1';\r
        when COND_NEVER =>\r
                cond_met := '0';\r
+       when others => null;\r
        end case;\r
-       \r
+       
+       cond_met := cond_met and (alu_state.alu_jmp xnor alu_state.brpr);
+\r
        case op_group is\r
        when ADDSUB_OP =>\r
                result_v := add_result;\r
@@ -95,9 +112,29 @@ begin
        when XOR_OP =>\r
                result_v := xor_result;\r
        when SHIFT_OP =>\r
-               result_v := shift_result;\r
+               result_v := shift_result;
+        when LDST_OP =>
+                res_prod := '0';
+                mem_op := '1';
+                if op_detail(IMM_OPT) = '1' then
+                        result_v.result := right_operand;
+                        res_prod := '1';
+                        mem_op := '0';
+                end if;
+                if op_detail(ST_OPT) = '1' then
+                        right <= displacement;
+                        mem_en := '1';
+                end if;
+       when JMP_OP =>
+               if op_detail(JMP_REG_OPT) = '0' then
+                       left <= prog_cnt;
+               end if;
+               result_v.alu_jmp := '1';
+       when JMP_ST_OP => null;\r
        end case;\r
        \r
+\r
+       result_v.status.zero := '0';\r
        if result_v.result = REG_ZERO then\r
                result_v.status.zero := '1';\r
        end if;\r
@@ -108,33 +145,14 @@ begin
                result_v.status := alu_state.status;\r
        end if;\r
        \r
-       result_v.new_val := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
-       result_v.mem_en := mem_en and cond_met;\r
-       \r
+       result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
+       result_v.mem_en := mem_en and cond_met;
+        result_v.mem_op := mem_op and cond_met;
+       result_v.alu_jmp := alu_jmp and cond_met;
+        \r
        alu_result <= result_v;\r
        \r
 end process calc; \r
 \r
 end architecture behaviour;\r
 \r
-configuration alu_cfg of alu is\r
-\r
-       for behaviour\r
-               for add_inst : exec_op \r
-                       use entity work.exec_op(add_op);\r
-               end for;\r
-               for and_inst : exec_op \r
-                       use entity work.exec_op(and_op);\r
-               end for;\r
-               for or_inst : exec_op\r
-                       use entity work.exec_op(or_op);\r
-               end for;\r
-               for xor_inst : exec_op\r
-                       use entity work.exec_op(xor_op);\r
-               end for;\r
-               for shift_inst : exec_op\r
-                       use entity work.exec_op(shift_op);\r
-               end for;\r
-       end for;\r
-               \r
-end configuration alu_cfg;\r