-Split rombios32.c up into multiple files.
-
-Support parsing of linuxbios/coreboot table.
-
-Do a pci scan for ide controllers - don't just assume ISA ports are
-available.
-
Review changes committed to coreboot, virtualbox, qemu, kvm, and bochs
cvs tip.
- * bochs cvs (1.209) -- all changes synched
- * coreboot (r3348): 1.163 -- no noteworthy enhancements
- * qemu (r4675): 1.207 -- supports >4Gig memory
- * kvm (45a442c): 1.182 -- >4gig, e820 vmx pages, enable cache?
- * virtualbox (r9404): 1.176 -- f11/f12 kbd, lots of mouse changes,
- logo, set text mode?, int 1589, floppy data rate?,
- dummy_isr_function, int19 calls post
-
-Look into ways to reduce stack usage. Alter ISRs so that they do not
-enable irqs. Only call out to other bios functions after minimizing
-stack usage.
-
-Audit all sti/cli calls. Audit all call16 calls to make sure flags is
-setup properly with respect to irqs.
-
-Audit statements where a 32bit intermediary changes meaning of a 16bit
-comparison.
-
-Code assumes ebda segment is static - it doesn't read 0x40e.
+ * bochs cvs (20100104):
+ -- changes synched
+ * coreboot (r3348): (bochs 20060708)
+ -- no noteworthy enhancements
+ * qemu - now uses SeaBIOS
+ * kvm - now uses SeaBIOS
+ * virtualbox (r13560): (bochs 20061231)
+ -- lots of mouse changes, logo, scsi/etherboot hooks,
+ floppy data rate?, int19 calls post
The __call16 code does a long jump to the interrupt trampolines - this
is unnecessary.
-Fix makefiles so that they rebuild the required files automatically.
-
-Cleanup setting of ES on GET/SET_BDA
-
-Possibly implement 32bit pcibios support.
-
-Allow one to select adding 32 bit code to 0xf000 or in a separate
-location.
-
-Look at integrating the lgpl vgabios into tree.
+Support PCIv3 roms? Add support for PCI "configuration code"
+extensions?
-Try generating bios tables at compile time.
+Possibly add option to eliminate tsc based delays on emulators.
-Move e820 map generation to post time (just have e820 code copy pre
-made tables back to user).
+Possibly support sending debug information over EHCI debug port.