cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only doing a

[coreboot.git] / NEWS

diff --git a/NEWS b/NEWS
index 1e2feb71d22285f7314024f0ecae1c1d1c7d9b09..770df4dd98c578449b78e23e7a4d1ae662b05111 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -1,3 +1,35 @@
+- 2.0.0
+  - this NEWS file is neglected in favor of the svn commit logs.
+    See http://tracker.coreboot.org/
+- 1.1.8
+  - Store everything in arch
+- 1.1.7
+  - The configuration language has been cleaned up.  No more link keyword.
+  - Everything is now in the device tree.
+  - The static and dynamic device trees have been unified
+  - Support for setting the pci subsystem vendor and pci subsystem device has been added.
+  - 64bit resource support
+  - Generic smbus support
+- 1.1.6
+  - pnp/superio devices are now handled cleanly with very little code
+  - Initial support for finding x86 BIST errors
+  - static resource assignments can now be specified in Config.lb
+  - special VGA I/O decode now should work
+  - added generic PCI error reporting enables
+  - build_opt_tbl now generates a header that allows cmos settings to
+    be read from romcc compiled code.
+  - split IORESOURCE_SET into IORESOURCE_ASSIGNED and IORESOURCE_STORED
+  - romcc now gracesfully handles function pointers instead of dying mysteriously
+  - First regression test in amdk8/raminit_test
+- 1.1.5
+  - O2, enums, and switch statements work in romcc
+  - Support for compiling romcc on non x86 platforms
+  - new romc options -msse and -mmmx for specifying extra registers to use
+  - Bug fixes to device the device disable/enable framework and an amd8111 implementation
+  - Move the link specification to the chip specification instead of the path
+  - Allow specifying devices with internal bridges.
+  - Initial via epia support
+  - Opteron errata fixes
 - 1.1.4
   Major restructuring of hypertransport handling.
   Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically