3a_asm: FEATURE/FIX: proper line numbers on parsing error

[calu.git] / 2_isa / logic.ptex

diff --git a/2_isa/logic.ptex b/2_isa/logic.ptex
index aa97db88f7332c1f34d43d9f5b375455e5d79ba5..3d24966a7d827a1d9720f5ad8da8f278f85a3f19 100644 (file)
--- a/2_isa/logic.ptex
+++ b/2_isa/logic.ptex
@@ -1,26 +1,34 @@
 
 
-ins ('32', 'and', 'And', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
+ins ('32', 'and', 'And', '4 | 5 | 4 | 4 | 4 | 10 | 1',
+'Conditions | OpCode (00100) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
 
 # ins ('32', 'andi', 'And im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
 
-ins ('32', 'andx', 'And im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | D');
+ins ('32', 'andx', 'And im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
+'Conditions | OpCode (00101) | Register Destination| Immediate | H/L | F | D');
 
-ins ('32', 'or', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | D');
+ins ('32', 'or', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1',
+'Conditions | OpCode (00110) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
 
 # ins ('32', 'ori', 'Or im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
 
-ins ('32', 'orx', 'Or im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | D');
+ins ('32', 'orx', 'Or im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
+'Conditions | OpCode (00111) | Register Destination| Immediate | H/L | F | D');
 
-ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | D');
+ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1',
+'Conditions | OpCode (01000) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
 
 # ins ('32', 'xori', 'Xor im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
 
-ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | D',
-'', '', '', 'not rD - xorxlf rD, rD, 0xFFFF');
+ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
+'Conditions | OpCode (01001) | Register Destination| Immediate | H/L | F | D',
+'', '', '', 'not-Negate-3/1111111111111111-4/0-5/1');
 
-ins ('32', 'l{l,r}s', 'left/right shift', '4 | 5 | 4 | 4 | 5 | 6 | 1 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | l/r | A C | D',
-'',' | Will change if C is set | | ');
+ins ('32', 'shift', 'left/right shift', '4 | 5 | 4 | 4 | 5 | 6 | 1 | 1 | 1 | 1',
+'Conditions | OpCode (01010) | Register Destination|Register A (Source1)| Immediate | - | l/r | A | C | D',
+'',' | Will change if C is set | | ', '',
+'lls-left shift-6/0-7/0|lrs-right shift-6/1-7/0|ars-arithmetic right shift-6/1-7/1-8/0');
 
 #plaintext ('\\mbox{}\\\\ \\todo{lls und lrs zusammenfassen $\rightarrow$ ein bit entscheidet fuer shift nach links oder rechts}');