'Conditions | OpCode (00111) | Register Destination| Immediate | H/L | F | D');
ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 10 | 1',
-'Conditions | OpCode (01001) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
+'Conditions | OpCode (01000) | Register Destination|Register A (Source1)| Register B (Source2) | - | D');
# ins ('32', 'xori', 'Xor im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1',
-'Conditions | OpCode (01010) | Register Destination| Immediate | H/L | F | D',
+'Conditions | OpCode (01001) | Register Destination| Immediate | H/L | F | D',
'', '', '', 'not-Negate-3/1111111111111111-4/0-5/1');
-ins ('32', 'l{l,r}s', 'left/right shift', '4 | 5 | 4 | 4 | 5 | 6 | 1 | 1 | 1 | 1',
-'Conditions | OpCode (01011) | Register Destination|Register A (Source1)| Immediate | - | l/r | A C | D',
-'',' | Will change if C is set | | ');
+ins ('32', 'shift', 'left/right shift', '4 | 5 | 4 | 4 | 5 | 6 | 1 | 1 | 1 | 1',
+'Conditions | OpCode (01010) | Register Destination|Register A (Source1)| Immediate | - | l/r | A | C | D',
+'',' | Will change if C is set | | ', '',
+'lls-left shift-6/0-7/0|lrs-right shift-6/1-7/0|ars-arithmetic right shift-6/1-7/1-8/0');
#plaintext ('\\mbox{}\\\\ \\todo{lls und lrs zusammenfassen $\rightarrow$ ein bit entscheidet fuer shift nach links oder rechts}');