\section{Conditions}
+Every instruction can be predicated with a condition that will prevent the execution\footnote{The instruction will be executed, but no changes occur.} of the instruction iff the condition is not met. A list of available conditions, including the suffixes for the instruction, is shown in table~\ref{tab:conds}
+
+Above and below are for unsigned values. Greater and less for signed values.\\
+\textbf{Note:} The definition of tests of unsigned values (in the context of bits which will be tested) depends on the ISA. x86, AMD64 and AVR defines below (unsigned lower) as carry not set. ARM on the other hand defines below as carry set. We will follow the definition of arm in this manner.
+
\begin{table}[ht]
\centering
\begin{tabular}{|c|c|c|c|}\hline
- Bitcode & Condition & Bits to test & suffixes \\ \hline
- 0000 & equal / zero & ZF = 0 & eq, zs \\ \hline
- 0001 & not equal / not zero & ZF = 1 & neq, nz \\ \hline
- 0010 & not overflow & OF = 0 & no \\ \hline
- 0011 & overflow & OF = 1 & ov \\ \hline
- 0100 & not carry / below & CF = 0 & nc, bl \\ \hline
- 0101 & carry / above or equal & CF = 1 & cs, ae \\ \hline
- 0110 & not signed / not neg. & SF = 0 & ns, nn \\ \hline
- 0111 & signed / neg. & SF = 1 & ss, ns \\ \hline
- 1000 & above & (CF == 0 $\wedge$ ZF == 0) & ab \\ \hline
- 1001 & below or equal & (CF == 1 $\vee$ ZF == 1) & be \\ \hline
- 1010 & greater than or equal & SF == OF & ge \\ \hline
- 1011 & less than & SF != OF & lt \\ \hline
- 1100 & greater than & (ZF == 0 $\wedge$ SF == OF) & gt \\ \hline
- 1101 & less than or equal & (ZF == 1 $\vee$ SF != OF) & le \\ \hline
- 1110 & never & & nv \\ \hline
- 1111 & always & & \texttt{none} \\ \hline
+ \textbf{Bitcode}&\textbf{Condition}& \textbf{Bits to test} &\textbf{suffixes}\\\hline
+ 0000 & not equal / not zero & ZF = 0 & nq, nz \\ \hline
+ 0001 & equal / zero & ZF = 1 & eq, zs \\ \hline
+ 0010 & not overflow & OF = 0 & no \\ \hline
+ 0011 & overflow & OF = 1 & ov \\ \hline
+ 0100 & not carry / above or eq. & CF = 0 & nc, ae \\ \hline
+ 0101 & carry / below & CF = 1 & cs, bl \\ \hline
+ 0110 & not signed / not neg. & SF = 0 & ns, nn \\ \hline
+ 0111 & signed / neg. & SF = 1 & ss, ns \\ \hline
+ 1000 & above & (CF == 0 $\wedge$ ZF == 0) & ab \\ \hline
+ 1001 & below or equal & (CF == 1 $\vee$ ZF == 1) & be \\ \hline
+ 1010 & greater than or equal & SF == OF & ge \\ \hline
+ 1011 & less than & SF != OF & lt \\ \hline
+ 1100 & greater than & (ZF == 0 $\wedge$ SF == OF) & gt \\ \hline
+ 1101 & less than or equal & (ZF == 1 $\vee$ SF != OF) & le \\ \hline
+ 1110 & always & & \texttt{none} \\ \hline
+ 1111 & never & & nv \\ \hline
\end{tabular}
- \caption{codierung von conditions WARNING! may contain BUGS!!}
+ \caption{coding of conditions}
+ \label{tab:conds}
\end{table}
-\begin{table}
+%note: it seams that the definition of conditions on unsigned values depend on the instruction set. below is CF = 1 by x86/amd64 and avr, CF = 0 by arm. when cmp is defined as cmp r1, r2 == r1-r2 == is r1 COND r2 then arm looks more saner. the conditons marked with a X in the bitcode are open for change because of this unclear situation \Large{RFC} \normalsize
+
+\begin{table}[hpt]
\centering
\begin{tabular}{|l|c|c|c|c|} \hline
- Bit & 3 & 2 & 1 & 0 \\ \hline
- Flag & SF & CF & OF & ZF \\ \hline
+ \textbf{Bit} & 3 & 2 & 1 & 0 \\ \hline
+ \textbf{Flag}& SF & CF & OF & ZF \\ \hline
\end{tabular}
- \caption{billig PSW bitorder}
+ \caption{Bits in the PSW}
\end{table}
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