uart: swap status with config half word

[calu.git] / 2_isa / arith.ptex

diff --git a/2_isa/arith.ptex b/2_isa/arith.ptex
index 5abb0aca848bad25b6a986a49ef8168fbd5bc506..b17ed92ab8a10facaa1bc3d26aa4ff3fac2b5e2b 100644 (file)
--- a/2_isa/arith.ptex
+++ b/2_isa/arith.ptex
@@ -1,20 +1,22 @@
 ins ('32', 'add', 'Add',
-'4 | 5 | 4 | 4 | 4 | 10 | 1',
-'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C',
-'Adds Register A and Register B and save result in Register Destination \\\\
-When bit C is set, the content of the carry flag is also added.',
-'is set to the MSB of the result | is set if addition has a carry out | is set if a overflow occured | is set if the result is zero ',
+'4 | 5 | 4 | 4 | 4 | 9 | 1 | 1',
+'Conditions | OpCode (00000) | Register Destination|Register A (Source1)| Register B (Source2) | - | C | D',
+'Adds register A and register B and saves the result in register Destination',
+'is set to the MSB of the result | is set if addition has a carry out | is set if a overflow occurred | is set if the result is zero ',
 'add  r0, r2, r4 ; add low bytes
  addc r1, r3, r5 ; add high bytes');
 
-ins ('32', 'addi', 'Add im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | S | C');
+ins ('32', 'addi', 'Add im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode (00010) | Register Destination|Register A (Source1)| Immediate | S | C | D',
+'Adds register A and immediate and saves the result in register Destination',
+'','',
+'mov-Move-4/000000000000-5/0-6/0-7/0');
 
-ins ('32', 'addx', 'Add im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');
+# ins ('32', 'addx', 'Add im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');
 
-ins ('32', 'sub', 'Sub', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C');
+ins ('32', 'sub', 'Sub', '4 | 5 | 4 | 4 | 4 | 9 | 1 | 1', 'Conditions | OpCode (00001) | Register Destination|Register A (Source1)| Register B (Source2) | - | C | D');
 
-ins ('32', 'subi', 'Sub im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | S | C');
+ins ('32', 'subi', 'Sub im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode (00011) | Register Destination|Register A (Source1)| Immediate | S | C | D');
 
-ins ('32', 'subx', 'Sub im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');
+# ins ('32', 'subx', 'Sub im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');