+
+/****************************************************************
+ * extbios
+ ****************************************************************/
+
+static void
+clext_101280(struct bregs *regs)
+{
+ u16 crtc_addr = stdvga_get_crtc();
+ outb(0x27, crtc_addr);
+ u8 v = inb(crtc_addr + 1);
+ if (v == 0xa0)
+ // 5430
+ regs->ax = 0x0032;
+ else if (v == 0xb8)
+ // 5446
+ regs->ax = 0x0039;
+ else
+ regs->ax = 0x00ff;
+ regs->bx = 0x00;
+ return;
+}
+
+static void
+clext_101281(struct bregs *regs)
+{
+ // XXX
+ regs->ax = 0x0100;
+}
+
+static void
+clext_101282(struct bregs *regs)
+{
+ u16 crtc_addr = stdvga_get_crtc();
+ outb(0x27, crtc_addr);
+ regs->al = inb(crtc_addr + 1) & 0x03;
+ regs->ah = 0xAF;
+}
+
+static void
+clext_101285(struct bregs *regs)
+{
+ regs->al = cirrus_get_memsize();
+}
+
+static void
+clext_10129a(struct bregs *regs)
+{
+ regs->ax = 0x4060;
+ regs->cx = 0x1132;
+}
+
+extern void a0h_callback(void);
+ASM16(
+ // fatal: not implemented yet
+ "a0h_callback:"
+ "cli\n"
+ "hlt\n"
+ "retf");
+
+static void
+clext_1012a0(struct bregs *regs)
+{
+ struct cirrus_mode_s *table_g = cirrus_get_modeentry(regs->al & 0x7f);
+ regs->ah = (table_g ? 1 : 0);
+ regs->si = 0xffff;
+ regs->di = regs->ds = regs->es = regs->bx = (u32)a0h_callback;
+}
+
+static void
+clext_1012a1(struct bregs *regs)
+{
+ regs->bx = 0x0e00; // IBM 8512/8513, color
+}
+
+static void
+clext_1012a2(struct bregs *regs)
+{
+ regs->al = 0x07; // HSync 31.5 - 64.0 kHz
+}
+
+static void
+clext_1012ae(struct bregs *regs)
+{
+ regs->al = 0x01; // High Refresh 75Hz
+}
+
+static void
+clext_1012XX(struct bregs *regs)
+{
+ debug_stub(regs);
+}
+
+void
+clext_1012(struct bregs *regs)
+{
+ switch (regs->bl) {
+ case 0x80: clext_101280(regs); break;
+ case 0x81: clext_101281(regs); break;
+ case 0x82: clext_101282(regs); break;
+ case 0x85: clext_101285(regs); break;
+ case 0x9a: clext_10129a(regs); break;
+ case 0xa0: clext_1012a0(regs); break;
+ case 0xa1: clext_1012a1(regs); break;
+ case 0xa2: clext_1012a2(regs); break;
+ case 0xae: clext_1012ae(regs); break;
+ default: clext_1012XX(regs); break;
+ }
+}
+
+
+/****************************************************************
+ * vesa calls
+ ****************************************************************/
+
+void
+clext_list_modes(u16 seg, u16 *dest, u16 *last)
+{
+ int i;
+ for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist) && dest<last; i++) {
+ SET_FARVAR(seg, *dest, GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
+ dest++;
+ }
+ stdvga_list_modes(seg, dest, last);
+}
+
+static u8
+cirrus_get_bpp_bytes(void)
+{
+ outb(0x07, VGAREG_SEQU_ADDRESS);
+ u8 v = inb(VGAREG_SEQU_DATA) & 0x0e;
+ if (v == 0x06)
+ v &= 0x02;
+ v >>= 1;
+ if (v != 0x04)
+ v++;
+ return v;
+}
+
+static void
+cirrus_set_line_offset(u16 new_line_offset)
+{
+ new_line_offset /= 8;
+ u16 crtc_addr = stdvga_get_crtc();
+ outb(0x13, crtc_addr);
+ outb(new_line_offset, crtc_addr + 1);
+
+ outb(0x1b, crtc_addr);
+ u8 v = inb(crtc_addr + 1);
+ outb(((new_line_offset & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
+}
+
+static u16
+cirrus_get_line_offset(void)
+{
+ u16 crtc_addr = stdvga_get_crtc();
+ outb(0x13, crtc_addr);
+ u8 reg13 = inb(crtc_addr + 1);
+ outb(0x1b, crtc_addr);
+ u8 reg1b = inb(crtc_addr + 1);
+
+ return (((reg1b & 0x10) << 4) + reg13) * 8;
+}
+
+static void
+cirrus_set_start_addr(u32 addr)
+{
+ u16 crtc_addr = stdvga_get_crtc();
+ outb(0x0d, crtc_addr);
+ outb(addr, crtc_addr + 1);
+
+ outb(0x0c, crtc_addr);
+ outb(addr>>8, crtc_addr + 1);
+
+ outb(0x1d, crtc_addr);
+ u8 v = inb(crtc_addr + 1);
+ outb(((addr & 0x0800) >> 4) | (v & 0x7f), crtc_addr + 1);
+
+ outb(0x1b, crtc_addr);
+ v = inb(crtc_addr + 1);
+ outb(((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7) | (v & 0xf2)
+ , crtc_addr + 1);
+}
+
+static u32
+cirrus_get_start_addr(void)
+{
+ u16 crtc_addr = stdvga_get_crtc();
+ outb(0x0c, crtc_addr);
+ u8 b2 = inb(crtc_addr + 1);
+
+ outb(0x0d, crtc_addr);
+ u8 b1 = inb(crtc_addr + 1);
+
+ outb(0x1b, crtc_addr);
+ u8 b3 = inb(crtc_addr + 1);
+
+ outb(0x1d, crtc_addr);
+ u8 b4 = inb(crtc_addr + 1);
+
+ return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
+ | ((b4 & 0x80) << 12));
+}
+
+static void
+cirrus_vesa_05h(struct bregs *regs)
+{
+ if (regs->bl > 1)
+ goto fail;
+ if (regs->bh == 0) {
+ // set mempage
+ if (regs->dx >= 0x100)
+ goto fail;
+ outw((regs->dx << 8) | (regs->bl + 9), VGAREG_GRDC_ADDRESS);
+ } else if (regs->bh == 1) {
+ // get mempage
+ outb(regs->bl + 9, VGAREG_GRDC_ADDRESS);
+ regs->dx = inb(VGAREG_GRDC_DATA);
+ } else
+ goto fail;
+
+ regs->ax = 0x004f;
+ return;
+fail:
+ regs->ax = 0x014f;
+}
+
+static void
+cirrus_vesa_06h(struct bregs *regs)
+{
+ if (regs->bl > 2) {
+ regs->ax = 0x0100;
+ return;
+ }
+
+ if (regs->bl == 0x00) {
+ cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
+ } else if (regs->bl == 0x02) {
+ cirrus_set_line_offset(regs->cx);
+ }
+
+ u32 v = cirrus_get_line_offset();
+ regs->cx = v / cirrus_get_bpp_bytes();
+ regs->bx = v;
+ regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
+ regs->ax = 0x004f;
+}
+
+static void
+cirrus_vesa_07h(struct bregs *regs)
+{
+ if (regs->bl == 0x80 || regs->bl == 0x00) {
+ u32 addr = (cirrus_get_bpp_bytes() * regs->cx
+ + cirrus_get_line_offset() * regs->dx);
+ cirrus_set_start_addr(addr / 4);
+ } else if (regs->bl == 0x01) {
+ u32 addr = cirrus_get_start_addr() * 4;
+ u32 linelength = cirrus_get_line_offset();
+ regs->dx = addr / linelength;
+ regs->cx = (addr % linelength) / cirrus_get_bpp_bytes();
+ } else {
+ regs->ax = 0x0100;
+ return;
+ }
+
+ regs->ax = 0x004f;
+}
+
+static void
+cirrus_vesa_10h(struct bregs *regs)
+{
+ if (regs->bl == 0x00) {
+ regs->bx = 0x0f30;
+ regs->ax = 0x004f;
+ return;
+ }
+ if (regs->bl == 0x01) {
+ SET_BDA(vbe_flag, regs->bh);
+ regs->ax = 0x004f;
+ return;
+ }
+ if (regs->bl == 0x02) {
+ regs->bh = GET_BDA(vbe_flag);
+ regs->ax = 0x004f;
+ return;
+ }
+ regs->ax = 0x014f;
+}
+
+static void
+cirrus_vesa_not_handled(struct bregs *regs)
+{
+ debug_stub(regs);
+ regs->ax = 0x014f;
+}
+