+static void
+cirrus_set_line_offset(u16 new_line_offset)
+{
+ u16 crtc_addr = cirrus_get_crtc();
+ outb(0x13, crtc_addr);
+ outb(new_line_offset / 8, crtc_addr + 1);
+
+ outb(0x1b, crtc_addr);
+ u8 v = inb(crtc_addr + 1);
+ outb((((new_line_offset / 8) & 0x100) >> 4) | (v & 0xef), crtc_addr + 1);
+}
+
+static u16
+cirrus_get_line_offset(void)
+{
+ u16 crtc_addr = cirrus_get_crtc();
+ outb(0x13, crtc_addr);
+ u8 reg13 = inb(crtc_addr + 1);
+ outb(0x1b, crtc_addr);
+ u8 reg1b = inb(crtc_addr + 1);
+
+ return (((reg1b << 4) & 0x100) + reg13) * 8;
+}
+
+static u16
+cirrus_get_line_offset_entry(struct cirrus_mode_s *table_g)
+{
+ u16 *crtc = GET_GLOBAL(table_g->crtc);
+
+ u16 *c = crtc;
+ u16 reg13;
+ for (;;) {
+ reg13 = GET_GLOBAL(*c);
+ if ((reg13 & 0xff) == 0x13)
+ break;
+ c++;
+ }
+ reg13 >>= 8;
+
+ c = crtc;
+ u16 reg1b;
+ for (;;) {
+ reg1b = GET_GLOBAL(*c);
+ if ((reg1b & 0xff) == 0x1b)
+ break;
+ c++;
+ }
+ reg1b >>= 8;
+
+ return (((reg1b << 4) & 0x100) + reg13) * 8;
+}
+
+static void
+cirrus_set_start_addr(u32 addr)
+{
+ u16 crtc_addr = cirrus_get_crtc();
+ outb(0x0d, crtc_addr);
+ outb(addr, crtc_addr + 1);
+
+ outb(0x0c, crtc_addr);
+ outb(addr>>8, crtc_addr + 1);
+
+ outb(0x1d, crtc_addr);
+ u8 v = inb(crtc_addr + 1);
+ outb(((addr & 0x0800) >> 4) | (v & 0x7f), crtc_addr + 1);
+
+ outb(0x1b, crtc_addr);
+ v = inb(crtc_addr + 1);
+ outb(((addr & 0x0100) >> 8) | ((addr & 0x0600) >> 7) | (v & 0xf2)
+ , crtc_addr + 1);
+}
+
+static u32
+cirrus_get_start_addr(void)
+{
+ u16 crtc_addr = cirrus_get_crtc();
+ outb(0x0c, crtc_addr);
+ u8 b2 = inb(crtc_addr + 1);
+
+ outb(0x0d, crtc_addr);
+ u8 b1 = inb(crtc_addr + 1);
+
+ outb(0x1b, crtc_addr);
+ u8 b3 = inb(crtc_addr + 1);
+
+ outb(0x1d, crtc_addr);
+ u8 b4 = inb(crtc_addr + 1);
+
+ return (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
+ | ((b4 & 0x80) << 12));
+}
+
+static void
+cirrus_vesa_00h(struct bregs *regs)
+{
+ u16 seg = regs->es;
+ struct vbe_info *info = (void*)(regs->di+0);
+
+ if (GET_FARVAR(seg, info->signature) == VBE2_SIGNATURE) {
+ SET_FARVAR(seg, info->oem_revision, 0x0100);
+ SET_FARVAR(seg, info->oem_vendor_string,
+ SEGOFF(get_global_seg(), (u32)VBE_VENDOR_STRING));
+ SET_FARVAR(seg, info->oem_product_string,
+ SEGOFF(get_global_seg(), (u32)VBE_PRODUCT_STRING));
+ SET_FARVAR(seg, info->oem_revision_string,
+ SEGOFF(get_global_seg(), (u32)VBE_REVISION_STRING));
+ }
+ SET_FARVAR(seg, info->signature, VESA_SIGNATURE);
+
+ SET_FARVAR(seg, info->version, 0x0200);
+
+ SET_FARVAR(seg, info->oem_string
+ , SEGOFF(get_global_seg(), (u32)VBE_OEM_STRING));
+ SET_FARVAR(seg, info->capabilities, 0);
+ SET_FARVAR(seg, info->total_memory, cirrus_get_memsize());
+
+ u16 *destmode = (void*)info->reserved;
+ SET_FARVAR(seg, info->video_mode, SEGOFF(seg, (u32)destmode));
+ int i;
+ for (i=0; i<ARRAY_SIZE(cirrus_vesa_modelist); i++)
+ SET_FARVAR(seg, destmode[i]
+ , GET_GLOBAL(cirrus_vesa_modelist[i].vesamode));
+ SET_FARVAR(seg, destmode[i], 0xffff);
+
+ regs->ax = 0x004f;
+}
+
+static u32 cirrus_lfb_addr VAR16;
+
+static void
+cirrus_vesa_01h(struct bregs *regs)
+{
+ u16 mode = cirrus_vesamode_to_mode(regs->cx & 0x3fff);
+ if (!mode) {
+ regs->ax = 0x014f;
+ return;
+ }
+ struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
+ u32 lfb = GET_GLOBAL(cirrus_lfb_addr); // XXX
+ if ((regs->cx & 0x4000) && !lfb) {
+ regs->ax = 0x014f;
+ return;
+ }
+
+ u16 seg = regs->es;
+ struct vbe_mode_info *info = (void*)(regs->di+0);
+ memset_far(seg, info, 0, sizeof(*info));
+
+ SET_FARVAR(seg, info->mode_attributes, lfb ? 0xbb : 0x3b);
+ SET_FARVAR(seg, info->winA_attributes, 0x07);
+ SET_FARVAR(seg, info->winB_attributes, 0);
+ SET_FARVAR(seg, info->win_granularity, 16);
+ SET_FARVAR(seg, info->win_size, 64);
+ SET_FARVAR(seg, info->winA_seg, SEG_GRAPH);
+ SET_FARVAR(seg, info->winB_seg, 0x0);
+ SET_FARVAR(seg, info->win_func_ptr.segoff, 0x0); // XXX
+ u16 linesize = cirrus_get_line_offset_entry(table_g);
+ SET_FARVAR(seg, info->bytes_per_scanline, linesize);
+ SET_FARVAR(seg, info->xres, GET_GLOBAL(table_g->width));
+ u16 height = GET_GLOBAL(table_g->height);
+ SET_FARVAR(seg, info->yres, height);
+ SET_FARVAR(seg, info->xcharsize, 8);
+ SET_FARVAR(seg, info->ycharsize, 16);
+ SET_FARVAR(seg, info->planes, 1);
+ SET_FARVAR(seg, info->bits_per_pixel, GET_GLOBAL(table_g->depth));
+ SET_FARVAR(seg, info->banks, 1);
+ SET_FARVAR(seg, info->mem_model, GET_GLOBAL(table_g->vesacolortype));
+ SET_FARVAR(seg, info->bank_size, 0);
+
+ int pages = (cirrus_get_memsize() * 64 * 1024) / (height * linesize);
+ SET_FARVAR(seg, info->pages, pages - 1);
+ SET_FARVAR(seg, info->reserved0, 0);
+
+ SET_FARVAR(seg, info->red_size, GET_GLOBAL(table_g->vesaredmask));
+ SET_FARVAR(seg, info->red_pos, GET_GLOBAL(table_g->vesaredpos));
+ SET_FARVAR(seg, info->green_size, GET_GLOBAL(table_g->vesagreenmask));
+ SET_FARVAR(seg, info->green_pos, GET_GLOBAL(table_g->vesagreenpos));
+ SET_FARVAR(seg, info->blue_size, GET_GLOBAL(table_g->vesabluemask));
+ SET_FARVAR(seg, info->blue_pos, GET_GLOBAL(table_g->vesabluepos));
+ SET_FARVAR(seg, info->alpha_size, GET_GLOBAL(table_g->vesareservedmask));
+ SET_FARVAR(seg, info->alpha_pos, GET_GLOBAL(table_g->vesareservedpos));
+ u8 directcolor_info = GET_GLOBAL(table_g->bitsperpixel) <= 8;
+ SET_FARVAR(seg, info->directcolor_info, directcolor_info);
+
+ SET_FARVAR(seg, info->phys_base, lfb);
+
+ regs->ax = 0x004f;
+}
+
+static void
+cirrus_vesa_02h(struct bregs *regs)
+{
+ if (regs->bx & 0x3e00) {
+ regs->ax = 0x014f;
+ return;
+ }
+ if ((regs->bx & 0x1ff) < 0x100) {
+ // XXX - call legacy mode switch
+ regs->ax = 0x004f;
+ return;
+ }
+
+ u16 mode = cirrus_vesamode_to_mode(regs->cx & 0x3fff);
+ if (!mode) {
+ regs->ax = 0x014f;
+ return;
+ }
+ struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode);
+ cirrus_switch_mode(table_g);
+
+ if (!(regs->bx & 0x4000))
+ cirrus_enable_16k_granularity();
+ if (!(regs->bx & 0x8000))
+ cirrus_clear_vram(0);
+ SET_BDA(video_mode, mode);
+ SET_BDA(vbe_mode, regs->bx);
+
+ regs->ax = 0x004f;
+}
+
+static void
+cirrus_vesa_03h(struct bregs *regs)
+{
+ u16 mode = GET_BDA(vbe_mode);
+ if (!mode)
+ mode = GET_BDA(video_mode);
+ regs->bx = mode;
+
+ regs->ax = 0x004f;
+}
+
+// XXX - add cirrus_vesa_05h_farentry to vgaentry.S
+
+static void
+cirrus_vesa_05h(struct bregs *regs)
+{
+ if (regs->bl > 1)
+ goto fail;
+ if (regs->bh == 0) {
+ // set mempage
+ if (regs->dx >= 0x100)
+ goto fail;
+ outw((regs->dx << 8) | (regs->bl + 9), VGAREG_GRDC_ADDRESS);
+ } else if (regs->bh == 1) {
+ // get mempage
+ outb(regs->bl + 9, VGAREG_GRDC_ADDRESS);
+ regs->dx = inb(VGAREG_GRDC_DATA);
+ } else
+ goto fail;
+
+ regs->ax = 0x004f;
+ return;
+fail:
+ regs->ax = 0x014f;
+}
+
+static void
+cirrus_vesa_06h(struct bregs *regs)
+{
+ if (regs->bl > 2) {
+ regs->ax = 0x0100;
+ return;
+ }
+
+ if (regs->bl == 0x00) {
+ cirrus_set_line_offset(cirrus_get_bpp_bytes() * regs->cx);
+ } else if (regs->bl == 0x02) {
+ cirrus_set_line_offset(regs->cx);
+ }
+
+ u32 v = cirrus_get_line_offset();
+ regs->cx = v / cirrus_get_bpp_bytes();
+ regs->bx = v;
+ regs->dx = (cirrus_get_memsize() * 64 * 1024) / v;
+ regs->ax = 0x004f;
+}
+
+static void
+cirrus_vesa_07h(struct bregs *regs)
+{
+ if (regs->bl == 0x80 || regs->bl == 0x00) {
+ u32 addr = (cirrus_get_bpp_bytes() * regs->cx
+ + cirrus_get_line_offset() * regs->dx);
+ cirrus_set_start_addr(addr / 4);
+ } else if (regs->bl == 0x01) {
+ u32 addr = cirrus_get_start_addr() * 4;
+ u32 linelength = cirrus_get_line_offset();
+ regs->dx = addr / linelength;
+ regs->cx = (addr % linelength) / cirrus_get_bpp_bytes();
+ } else {
+ regs->ax = 0x0100;
+ return;
+ }
+
+ regs->ax = 0x004f;
+}
+
+static void
+cirrus_vesa_10h(struct bregs *regs)
+{
+ if (regs->bl == 0x00) {
+ regs->bx = 0x0f30;
+ regs->ax = 0x004f;
+ return;
+ }
+ if (regs->bl == 0x01) {
+ SET_BDA(vbe_flag, regs->bh);
+ regs->ax = 0x004f;
+ return;
+ }
+ if (regs->bl == 0x02) {
+ regs->bh = GET_BDA(vbe_flag);
+ regs->ax = 0x004f;
+ return;
+ }
+ regs->ax = 0x014f;
+}
+
+static void
+cirrus_vesa_not_handled(struct bregs *regs)
+{
+ debug_stub(regs);
+ regs->ax = 0x014f;
+}
+
+void
+cirrus_vesa(struct bregs *regs)
+{
+ switch (regs->al) {
+ case 0x00: cirrus_vesa_00h(regs); break;
+ case 0x01: cirrus_vesa_01h(regs); break;
+ case 0x02: cirrus_vesa_02h(regs); break;
+ case 0x03: cirrus_vesa_03h(regs); break;
+ case 0x05: cirrus_vesa_05h(regs); break;
+ case 0x06: cirrus_vesa_06h(regs); break;
+ case 0x07: cirrus_vesa_07h(regs); break;
+ case 0x10: cirrus_vesa_10h(regs); break;
+ default: cirrus_vesa_not_handled(regs); break;
+ }
+}
+
+
+/****************************************************************
+ * init
+ ****************************************************************/
+