+void probe_idregs_smsc(uint16_t port);
+void print_smsc_chips(void);
+
+/* winbond.c */
+void probe_idregs_winbond(uint16_t port);
+void print_winbond_chips(void);
+
+/* via.c */
+#ifdef PCI_SUPPORT
+void probe_idregs_via(uint16_t port);
+void print_via_chips(void);
+#endif
+
+/** Table of which config ports to probe for each Super I/O family. */
+static const struct {
+ void (*probe_idregs) (uint16_t port);
+ int ports[MAXNUMPORTS]; /* Signed, as we need EOT. */
+} superio_ports_table[] = {
+ {probe_idregs_ali, {0x3f0, 0x370, EOT}},
+ {probe_idregs_fintek, {0x2e, 0x4e, EOT}},
+ {probe_idregs_fintek_alternative, {0x2e, 0x4e, EOT}},
+ /* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */
+ {probe_idregs_ite, {0x25e, 0x2e, 0x4e, 0x370, EOT}},
+ {probe_idregs_nsc, {0x2e, 0x4e, 0x15c, 0x164e, EOT}},
+ /* I/O pairs on Nuvoton EC chips can be configured by firmware in
+ * addition to the following hardware strapping options. */
+ {probe_idregs_nuvoton, {0x164e, 0x2e, 0x4e, EOT}},
+ {probe_idregs_smsc, {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}},
+ {probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}},
+#ifdef PCI_SUPPORT
+ {probe_idregs_via, {0x3f0, EOT}},
+#endif
+ {probe_idregs_serverengines, {0x2e, EOT}},
+};
+
+/** Table of functions to print out supported Super I/O chips. */
+static const struct {
+ void (*print_list) (void);
+} vendor_print_functions[] = {
+ {print_ali_chips},
+ {print_fintek_chips},
+ {print_ite_chips},
+ {print_nsc_chips},
+ {print_nuvoton_chips},
+ {print_smsc_chips},
+ {print_winbond_chips},
+#ifdef PCI_SUPPORT
+ {print_via_chips},
+#endif
+ {print_serverengines_chips},
+};