-static const io_register_t ich4_gpio_registers[] = {
- { 0x00, 4, "GPIO_USE_SEL" },
- { 0x04, 4, "GP_IO_SEL" },
- { 0x08, 4, "RESERVED" },
- { 0x0c, 4, "GP_LVL" },
- { 0x10, 4, "RESERVED" },
- { 0x14, 4, "GPO_TTL" },
- { 0x18, 4, "GPO_BLINK" },
- { 0x1c, 4, "RESERVED" },
- { 0x20, 4, "RESERVED" },
- { 0x24, 4, "RESERVED" },
- { 0x28, 4, "RESERVED" },
- { 0x2c, 4, "GPI_INV" },
- { 0x30, 4, "GPIO_USE_SEL2" },
- { 0x34, 4, "GP_IO_SEL2" },
- { 0x38, 4, "GP_LVL2" },
- { 0x3C, 4, "RESERVED" }
-};
-
-static const io_register_t ich7_gpio_registers[] = {
- { 0x00, 4, "GPIO_USE_SEL" },
- { 0x04, 4, "GP_IO_SEL" },
- { 0x08, 4, "RESERVED" },
- { 0x0c, 4, "GP_LVL" },
- { 0x10, 4, "RESERVED" },
- { 0x14, 4, "RESERVED" },
- { 0x18, 4, "GPO_BLINK" },
- { 0x1c, 4, "RESERVED" },
- { 0x20, 4, "RESERVED" },
- { 0x24, 4, "RESERVED" },
- { 0x28, 4, "RESERVED" },
- { 0x2c, 4, "GPI_INV" },
- { 0x30, 4, "GPIO_USE_SEL2" },
- { 0x34, 4, "GP_IO_SEL2" },
- { 0x38, 4, "GP_LVL2" },
- { 0x3C, 4, "RESERVED" }
-};
-
-int print_gpios(struct pci_dev *sb)
-{
- int i, size;
- uint16_t gpiobase;
- const io_register_t *gpio_registers;
-
- printf("\n============= GPIOS =============\n\n");
-
- switch (sb->device_id) {
- case PCI_DEVICE_ID_INTEL_ICH7:
- case PCI_DEVICE_ID_INTEL_ICH7M:
- case PCI_DEVICE_ID_INTEL_ICH7DH:
- case PCI_DEVICE_ID_INTEL_ICH7MDH:
- gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
- gpio_registers = ich7_gpio_registers;
- size = ARRAY_SIZE(ich7_gpio_registers);
- break;
- case PCI_DEVICE_ID_INTEL_ICH4:
- case PCI_DEVICE_ID_INTEL_ICH4M:
- gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
- gpio_registers = ich4_gpio_registers;
- size = ARRAY_SIZE(ich4_gpio_registers);
- break;
- case PCI_DEVICE_ID_INTEL_ICH:
- case PCI_DEVICE_ID_INTEL_ICH0:
- gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
- gpio_registers = ich0_gpio_registers;
- size = ARRAY_SIZE(ich0_gpio_registers);
- break;
- case 0x1234: // Dummy for non-existent functionality
- printf("This southbridge does not have GPIOBASE.\n");
- return 1;
- default:
- printf("Error: Dumping GPIOs on this southbridge is not (yet) supported.\n");
- return 1;
- }
-
- printf("GPIOBASE = 0x%04x (IO)\n\n", gpiobase);
-
- for (i = 0; i < size; i++) {
- switch (gpio_registers[i].size) {
- case 4:
- printf("gpiobase+0x%04x: 0x%08x (%s)\n",
- gpio_registers[i].addr,
- inl(gpiobase+gpio_registers[i].addr),
- gpio_registers[i].name);
- break;
- case 2:
- printf("gpiobase+0x%04x: 0x%04x (%s)\n",
- gpio_registers[i].addr,
- inw(gpiobase+gpio_registers[i].addr),
- gpio_registers[i].name);
- break;
- case 1:
- printf("gpiobase+0x%04x: 0x%02x (%s)\n",
- gpio_registers[i].addr,
- inb(gpiobase+gpio_registers[i].addr),
- gpio_registers[i].name);
- break;
- }
- }
-
- return 0;
-}
-
-int print_rcba(struct pci_dev *sb)
-{
- int i, size = 0x4000;
- volatile uint8_t *rcba;
- uint32_t rcba_phys;
-
- printf("\n============= RCBA ==============\n\n");
-
- switch (sb->device_id) {
- case PCI_DEVICE_ID_INTEL_ICH7:
- case PCI_DEVICE_ID_INTEL_ICH7M:
- case PCI_DEVICE_ID_INTEL_ICH7DH:
- case PCI_DEVICE_ID_INTEL_ICH7MDH:
- rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
- break;
- case PCI_DEVICE_ID_INTEL_ICH:
- case PCI_DEVICE_ID_INTEL_ICH0:
- case PCI_DEVICE_ID_INTEL_ICH4:
- case PCI_DEVICE_ID_INTEL_ICH4M:
- printf("This southbridge does not have RCBA.\n");
- return 1;
- default:
- printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n");
- return 1;
- }
-
- rcba = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
- fd_mem, (off_t) rcba_phys);
-
- if (rcba == MAP_FAILED) {
- perror("Error mapping RCBA");
- exit(1);
- }
-
- printf("RCBA = 0x%08x (MEM)\n\n", rcba_phys);
-
- for (i = 0; i < size; i += 4) {
- if (*(uint32_t *)(rcba + i))
- printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(rcba + i));
- }
-
- munmap((void *)rcba, size);
- return 0;
-}
-
-int print_pmbase(struct pci_dev *sb)
-{
- int i, size = 0x80;
- uint16_t pmbase;
-
- printf("\n============= PMBASE ============\n\n");
-
- switch (sb->device_id) {
- case PCI_DEVICE_ID_INTEL_ICH7:
- case PCI_DEVICE_ID_INTEL_ICH7M:
- case PCI_DEVICE_ID_INTEL_ICH7DH:
- case PCI_DEVICE_ID_INTEL_ICH7MDH:
- pmbase = pci_read_word(sb, 0x40) & 0xfffc;
- break;
- case 0x1234: // Dummy for non-existent functionality
- printf("This southbridge does not have PMBASE.\n");
- return 1;
- default:
- printf("Error: Dumping PMBASE on this southbridge is not (yet) supported.\n");
- return 1;
- }
-
- printf("PMBASE = 0x%04x (IO)\n\n", pmbase);
-
- for (i = 0; i < size; i += 4) {
- printf("pmbase+0x%04x: 0x%08x\n", i, inl(pmbase + i));
- }
-
- return 0;
-}
-
-/*
- * (G)MCH MMIO Config Space
- */
-int print_mchbar(struct pci_dev *nb)
-{
- int i, size = (16 * 1024);
- volatile uint8_t *mchbar;
- uint32_t mchbar_phys;
-
- printf("\n============= MCHBAR ============\n\n");
-
- switch (nb->device_id) {
- case PCI_DEVICE_ID_INTEL_82945GM:
- mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
- break;
- case 0x1234: // Dummy for non-existent functionality
- printf("This northbrigde does not have MCHBAR.\n");
- return 1;
- default:
- printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
- return 1;
- }
-
- mchbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
- fd_mem, (off_t) mchbar_phys);
-
- if (mchbar == MAP_FAILED) {
- perror("Error mapping MCHBAR");
- exit(1);
- }
-
- printf("MCHBAR = 0x%08x (MEM)\n\n", mchbar_phys);
-
- for (i = 0; i < size; i += 4) {
- if (*(uint32_t *)(mchbar + i))
- printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i));
- }