-#define MCODECHECK(icnt) \
- if ((cd->mcodeptr + (icnt)) > (u1 *) cd->mcodeend) \
- cd->mcodeptr = (u1 *) codegen_increase(cd, cd->mcodeptr)
-
-/* M_INTMOVE:
- generates an integer-move from register a to b.
- if a and b are the same int-register, no code will be generated.
-*/
-
-#define M_INTMOVE(reg,dreg) \
- if ((reg) != (dreg)) { \
- x86_64_mov_reg_reg(cd, (reg),(dreg)); \
- }
-
-
-/* M_FLTMOVE:
- generates a floating-point-move from register a to b.
- if a and b are the same float-register, no code will be generated
-*/
-
-#define M_FLTMOVE(reg,dreg) \
- if ((reg) != (dreg)) { \
- x86_64_movq_reg_reg(cd, (reg),(dreg)); \
- }
-
-
-/* var_to_reg_xxx:
- this function generates code to fetch data from a pseudo-register
- into a real register.
- If the pseudo-register has actually been assigned to a real
- register, no code will be emitted, since following operations
- can use this register directly.
-
- v: pseudoregister to be fetched from
- tempregnum: temporary register to be used if v is actually spilled to ram
-
- return: the register number, where the operand can be found after
- fetching (this wil be either tempregnum or the register
- number allready given to v)
-*/
+#define M_AADD(a,b) M_LADD(a,b)
+#define M_AADD_IMM(a,b) M_LADD_IMM(a,b)
+#define M_ASUB_IMM(a,b) M_LSUB_IMM(a,b)
+
+#define M_ISUB_IMM32(a,b) emit_alul_imm32_reg(cd, ALU_SUB, (a), (b))
+
+#define M_LADD_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_ADD, (a), (b))
+#define M_LSUB_IMM32(a,b) emit_alu_imm32_reg(cd, ALU_SUB, (a), (b))
+
+#define M_AADD_IMM32(a,b) M_LADD_IMM32(a,b)
+
+#define M_ILEA(a,b,c) emit_leal_membase_reg(cd, (a), (b), (c))
+#define M_LLEA(a,b,c) emit_lea_membase_reg(cd, (a), (b), (c))
+#define M_ALEA(a,b,c) M_LLEA(a,b,c)
+
+#define M_INEG(a) emit_negl_reg(cd, (a))
+#define M_LNEG(a) emit_neg_reg(cd, (a))
+
+#define M_IAND(a,b) emit_alul_reg_reg(cd, ALU_AND, (a), (b))
+#define M_IOR(a,b) emit_alul_reg_reg(cd, ALU_OR, (a), (b))
+#define M_IXOR(a,b) emit_alul_reg_reg(cd, ALU_XOR, (a), (b))
+
+#define M_IAND_IMM(a,b) emit_alul_imm_reg(cd, ALU_AND, (a), (b))
+#define M_IOR_IMM(a,b) emit_alul_imm_reg(cd, ALU_OR, (a), (b))
+#define M_IXOR_IMM(a,b) emit_alul_imm_reg(cd, ALU_XOR, (a), (b))
+
+#define M_LAND(a,b) emit_alu_reg_reg(cd, ALU_AND, (a), (b))
+#define M_LOR(a,b) emit_alu_reg_reg(cd, ALU_OR, (a), (b))
+#define M_LXOR(a,b) emit_alu_reg_reg(cd, ALU_XOR, (a), (b))
+
+#define M_LAND_IMM(a,b) emit_alu_imm_reg(cd, ALU_AND, (a), (b))
+#define M_LOR_IMM(a,b) emit_alu_imm_reg(cd, ALU_OR, (a), (b))
+#define M_LXOR_IMM(a,b) emit_alu_imm_reg(cd, ALU_XOR, (a), (b))
+
+#define M_BSEXT(a,b) emit_movsbq_reg_reg(cd, (a), (b))
+#define M_SSEXT(a,b) emit_movswq_reg_reg(cd, (a), (b))
+#define M_ISEXT(a,b) emit_movslq_reg_reg(cd, (a), (b))
+
+#define M_BZEXT(a,b) emit_movzbq_reg_reg(cd, (a), (b))
+#define M_CZEXT(a,b) emit_movzwq_reg_reg(cd, (a), (b))
+
+#define M_ISLL_IMM(a,b) emit_shiftl_imm_reg(cd, SHIFT_SHL, (a), (b))
+#define M_ISRA_IMM(a,b) emit_shiftl_imm_reg(cd, SHIFT_SAR, (a), (b))
+#define M_ISRL_IMM(a,b) emit_shiftl_imm_reg(cd, SHIFT_SHR, (a), (b))
+
+#define M_LSLL_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SHL, (a), (b))
+#define M_LSRA_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SAR, (a), (b))
+#define M_LSRL_IMM(a,b) emit_shift_imm_reg(cd, SHIFT_SHR, (a), (b))
+
+#define M_TEST(a) emit_test_reg_reg(cd, (a), (a))
+#define M_ITEST(a) emit_testl_reg_reg(cd, (a), (a))
+
+#define M_LCMP(a,b) emit_alu_reg_reg(cd, ALU_CMP, (a), (b))
+#define M_LCMP_IMM(a,b) emit_alu_imm_reg(cd, ALU_CMP, (a), (b))
+#define M_LCMP_IMM_MEMBASE(a,b,c) emit_alu_imm_membase(cd, ALU_CMP, (a), (b), (c))
+#define M_LCMP_MEMBASE(a,b,c) emit_alu_membase_reg(cd, ALU_CMP, (a), (b), (c))
+#define M_LCMP_MEMINDEX(a,b,c,d,e) emit_alul_memindex_reg(cd, ALU_CMP, (b), (a), (c), (d), (e))
+
+#define M_ICMP(a,b) emit_alul_reg_reg(cd, ALU_CMP, (a), (b))
+#define M_ICMP_IMM(a,b) emit_alul_imm_reg(cd, ALU_CMP, (a), (b))
+#define M_ICMP_IMM32(a,b) emit_alul_imm32_reg(cd, ALU_CMP, (a), (b))
+#define M_ICMP_IMM_MEMBASE(a,b,c) emit_alul_imm_membase(cd, ALU_CMP, (a), (b), (c))
+#define M_ICMP_MEMBASE(a,b,c) emit_alul_membase_reg(cd, ALU_CMP, (a), (b), (c))
+#define M_ICMP_MEMINDEX(a,b,c,d,e) emit_alu_memindex_reg(cd, ALU_CMP, (b), (a), (c), (d), (e))
+
+#define M_ACMP(a,b) M_LCMP(a,b)
+
+#define M_BEQ(disp) emit_jcc(cd, CC_E, (disp))
+#define M_BNE(disp) emit_jcc(cd, CC_NE, (disp))
+#define M_BLT(disp) emit_jcc(cd, CC_L, (disp))
+#define M_BLE(disp) emit_jcc(cd, CC_LE, (disp))
+#define M_BGE(disp) emit_jcc(cd, CC_GE, (disp))
+#define M_BGT(disp) emit_jcc(cd, CC_G, (disp))