+/* This fine tunes the HT link settings, which were loaded by ROM strap. */
+static void host_ctrl_enable_k8m890(struct device *dev) {
+
+ /*
+ * Set PCI to HT outstanding requests to 03.
+ * Bit 4 32 AGP ADS Read Outstanding Request Number
+ */
+ pci_write_config8(dev, 0xa0, 0x13);
+
+ /*
+ * NVRAM I/O base at K8T890_NVRAM_IO_BASE
+ */
+
+ pci_write_config8(dev, 0xa2, (K8T890_NVRAM_IO_BASE >> 8));
+
+ /* Enable NVRAM and enable non-posted PCI writes. */
+ pci_write_config8(dev, 0xa1, 0x8f);
+
+ /* Arbitration control */
+ pci_write_config8(dev, 0xa5, 0x3c);
+
+ /* Arbitration control 2, Enable C2NOW delay to PSTATECTL */
+ pci_write_config8(dev, 0xa6, 0x83);
+
+}
+
+static const struct device_operations host_ctrl_ops_t = {